Stuart Burns

In the United States, there are 114 individuals named Stuart Burns spread across 35 states, with the largest populations residing in Texas, Virginia, Florida.

Public information about Stuart Burns

Resumes

Chief Of Staff

Location:

Washington, DC

Industry:

Government Administration

Work:

Rep Bill Posey
Chief of Staff Rep Michael Cloud
Chief of Staff Rep Brian Babin Jan 2015 - Aug 2018
Chief of Staff U.s. House of Representatives Jan 2011 - Dec 2014
Chief of Staff U.s Congressman Bill Posey U.s. House of Representatives Jan 2009 - Dec 2010
Deputy Chief of Staff U.s Congressman Bill Posey U.s. House of Representatives Jan 1995 - Apr 2009
Deputy Chief of Staff U.s Congressman Dave Weldon, M.d

Education:

King University 1984 - 1988
Bachelors, Bachelor of Arts, Political Science, History Northview High School

Skills:

Policy Analysis, Legislative Relations, Government, Public Policy, Politics, Public Speaking, Political Consulting, Fundraising, Nonprofits, Legislation, Political Campaigns, Legislative Research

Senior Govt Relations Representative

Location:

Washington, DC

Industry:

Government Relations

Work:

Am Assn of Orthopaedic Surgeons
Senior Govt Relations Representative American Assn of Orthopaedic Surgeons
Senior Government Releations Representative

Skills:

Government Relations

General Secretary - Imm Usa

Location:

3149 Highway 105 south, Boone, NC 28607

Industry:

Mining & Metals

Work:

International Miners Mission since Mar 1992
General Secretary South Africa Jul 1987 - Jul 1991
Africa Evangelical Fellowship Roxboro, NC 1977 - 1987
Moore Forest Industries

Education:

Johannesburg, South Africa
University of Tennessee, Nashville

Skills:

Budgets, Business Strategy, Community Outreach, Customer Service, Fundraising, Leadership, Leadership Development, Management, Microsoft Office, Microsoft Word, Nonprofits, Preaching, Public Speaking, Teaching, Strategic Planning, Team Building

Vice President - Risk Analyst Iii

Location:

Phoenix, AZ

Industry:

Financial Services

Work:

Bank of America
Vice President - Risk Analyst Iii Conseco Finance Aug 1997 - Dec 2002
Team Leader Zale Apr 1990 - Aug 1997
Assistant Authorizations Manager United States Marine Corps Mar 1985 - Feb 1993
Sergeant

Education:

Arizona State University 1984 - 1995
Bachelors, Criminal Justice, Political Science Arizona State University 1984 - 1994
Mesa Community College 1990 - 1993
Associates, Associate of Arts, Criminal Justice

Skills:

Team Building, Risk Management, Strategic Planning, Financial Risk, Process Improvement, Leadership, Customer Service, Management, Coaching, Small Business, Business Strategy, Team Leadership, Marketing, Public Speaking, Banking, Enterprise Risk Management, Leadership Development, Budgets, Business Process Improvement

Real Estate Agent

Work:

Burns Realty & Associates
Real Estate Agent City of St. Petersburg Dec 2009 - Jan 2013
Pool Supervisor

Education:

University of South Florida 2011
Bachelors, Psychology

Skills:

Cpr Certified, Public Speaking, First Aid, Customer Service, First Responder, Public Safety, Coaching, Training, Employee Training, Social Media, Nims, Disaster Response, Event Planning, Rescue, Ems, Firefighting, Hazardous Materials, Fire Protection, Fire Safety, Lifeguarding, Aed, Teaching

Pilot

Location:

Virginia Beach, VA

Industry:

Airlines/Aviation

Work:

Delta Air Lines
Pilot Us Navy Reserve
Pilot

Education:

Defense Acquisition University 2010 - 2013
Tidewater Community College 2009 - 2009
The University of New Mexico 1999 - 2003
Bachelors, Criminology

Skills:

Microsoft Office, Management, Microsoft Excel, Microsoft Word, Leadership, Research, Training, English, Defense, Navy, Program Management, Military, Dod, Operational Planning, Security Clearance, National Security, Military Experience, Military Operations, Aviation, Weapons

Stuart Burns

Location:

Minneapolis, MN

Industry:

Environmental Services

Work:

Savatree Jan 2019 - Dec 2019
Ground Crew

Food Service Worker

Location:

Cincinnati, OH

Work:

Trihealth
Food Service Worker

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Phones & Addresses

Name

Addresses

Phones

Stuart Burns

4601 Sycamore Valley Trl, Westport, KY 40077

502-222-3197

Stuart Burns

663 Ocean Ave E Cnn B H, Cannon Beach, OR 97110

503-436-2785

Stuart Burns

Chestertown, MD

410-778-6714

Stuart Burns

663 Ocean Ave, Cannon Beach, OR 97110

503-436-2785

Stuart Burns

663 Ocean, Portland, OR 97221

503-436-2785

Stuart Burns

Stoutland, MO

417-286-3452

Stuart M Burns

1420 Eaves Spring, Berwyn, PA 19312

610-647-5713

Stuart Burns

234 Morton Rd, Piperton, TN 38017

901-854-9653

Stuart Burns

324 Turk Hill Rd, Sears Corners, NY 10509

Stuart Burns

3510 SW Kanan Dr, Portland, OR 97221

503-329-9498

Stuart Burns

10017 Blue Coat Dr, Fairfax, VA 22030

703-385-7665

Stuart Burns

3630 Poplar St NE, Saint Petersburg, FL 33704

Stuart Burns

4204 Warren St, Davenport, IA 52806

563-391-4724

Stuart Burns

11405 Meath Dr, Fairfax, VA 22030

703-934-4728

Stuart Burns

4600 Monterey Oaks Blvd, Austin, TX 78749

512-750-8700

Stuart Burns

4646 E Gelding Dr, Phoenix, AZ 85032

Business Records

Name / Title

Company / Classification

Phones & Addresses

Stuart R Burns
Organizer

SYCAMORE VALLEY FARM, LLC

11717 Paramont Way, Prospect, KY 40059

Stuart Burns
Secretary, Director

Hotel Contracting Services, Inc
Hotel/Motel Operation Eating Place · Management Consulting Services

711 S Carson St, Carson City, NV 89701
2140 Professional Dr, Roseville, CA 95661
916-791-5700

Stuart Burns
Owner

Lee & Thomas Real Estate

237 Long Ln, Upper Darby, PA 19082
828-264-7771

Stuart Burns
Manager

Alcohol Alert Alaska, LLC
Whol Chemicals/Products

5305 N Star St, Anchorage, AK 99518
907-865-9120

Stuart R Burns

HOTEL CONTRACTING SERVICES, INC

2140 Professional Dr, Roseville, CA 95661

Stuart J. Burns
President

Bevs Inc Psc
Medical Doctor's Office · Veterinarian

1497 Millersburg Rd, Paris, KY 40361
PO Box 41, Paris, KY 40362
859-987-1646

Stuart J. Burns
Principal

Stuart Burns
Veterinary Services

1497 Millersburg Rd, Paris, KY 40361

Stuart R Burns
Manager

RAY'S KITILTR LLC
Business Services at Non-Commercial Site

4646 E Gelding, Phoenix, AZ 85032

Publications

Us Patents

Reactive Ion Etch Loading Measurement Technique

US Patent:

6268226, Jul 31, 2001

Filed:

Jun 30, 1999

Appl. No.:

9/345647

Inventors:

David Angell - Poughkeepsie NY
Stuart M. Burns - Brookfield CT
Waldemar W. Kocon - Wappingers Falls NY
Michael L. Passow - Pleasant Valley NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438 16

Abstract:

A process for estimating a critical dimension of a trench formed by etching a substrate. First, a regression model is constructed for estimating the critical dimension, in which principal component loadings and principal component scores are also calculated. Next, a substrate is etched and spectral data of the etching are collected. A new principal component score is then calculated using the spectral data and the principal component loadings. Finally, the critical dimension of the trench is estimated by applying the new principal component score to the regression model.

2F-Square Memory Cell For Gigabit Memory Applications

US Patent:

6040210, Mar 21, 2000

Filed:

Jan 26, 1998

Appl. No.:

9/013509

Inventors:

Stuart Mcallister Burns - Ridgefield CT
Hussein Ibrahim Hanafi - Goldens Bridge NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 218249
H01L 29788

US Classification:

438238

Abstract:

A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, each having a channel formed between source and drain regions. Two transistors are formed per pillar. This is achieved by forming two gates per pillar formed on opposite pillar sidewalls which are along the bitline direction. This forms two wordlines or gates per pillar arranged in the wordline direction. The source regions are self-aligned and located below the pillars. The source regions of adjacent bit lines are isolated from each other without increasing the cell size.

Anisotropic Nitride Etch Process With High Selectivity To Oxide And Photoresist Layers In A Damascene Etch Scheme

US Patent:

6461529, Oct 8, 2002

Filed:

Apr 26, 1999

Appl. No.:

09/299137

Inventors:

Diane C. Boyd - Lagrangeville NY
Stuart M. Burns - Brookfield CT
Hussein I. Hanafi - Basking Ridge NJ
Waldemar W. Kocon - Wappingers Falls NY
William C. Wille - Red Hook NY
Richard Wise - Beacon NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 213215

US Classification:

216 67, 216 72, 252 791, 438723, 438724, 438725, 438743, 438744

Abstract:

A process and etchant gas composition for anisotropically etching a trench in a silicon nitride layer of a multilayer structure. The etchant gas composition has an etchant gas including a polymerizing agent, a hydrogen source, an oxidant, and a noble gas diluent. The oxidant preferably includes a carbon-containing oxidant component and an oxidant-noble gas component. The fluorocarbon gas is selected from CF , C F , and C F ; the hydrogen source is selected from CHF , CH F , CH F, and H ; the oxidant is selected from CO, CO , and O ; and the noble gas diluent is selected from He, Ar, and Ne. The constituents are added in amounts to achieve an etchant gas having a high nitride selectivity to silicon oxide and photoresist. A power source, such as an RF power source, is applied to the structure to control the directionality of the high density plasma formed by exciting the etchant gas. The power source that controls the directionality of the plasma is decoupled from the power source used to excite the etchant gas.

Self-Aligned Diffused Source Vertical Transistors With Stack Capacitors In A 4F-Square Memory Cell Array

US Patent:

5929477, Jul 27, 1999

Filed:

Jan 22, 1997

Appl. No.:

8/792955

Inventors:

Stuart McAllister Burns - Ridgefield CT
Hussein Ibrahim Hanafi - Goldens Bridge NY
Jeffrey J. Welser - Greenwich CT
Waldemar Walter Kocon - Wappingers Fall NY
Howard Leo Kalter - Colchester VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29108
H01L 2976

US Classification:

257306

Abstract:

A densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of adjacent bitlines may be isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F. sup. 2 to be maintained. The array is suitable for Gbit DRAM applications because the stack capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof.

2F-Square Memory Cell For Gigabit Memory Applications

US Patent:

5990509, Nov 23, 1999

Filed:

Jan 22, 1997

Appl. No.:

8/787418

Inventors:

Stuart Mcallister Burns - Ridgefield CT
Hussein Jbrahim Hanafi - Goldens Bridge NY
Jeffrey J. Welser - Greenwich CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27108
H01L 2976
H01L 2994
H01L 29788

US Classification:

257296

Abstract:

Field Effect Transistors With Vertical Gate Side Walls And Method For Making Such Transistors

US Patent:

6593617, Jul 15, 2003

Filed:

Feb 19, 1998

Appl. No.:

09/026093

Inventors:

Diane C. Boyd - Lagrangeville NY
Stuart M. Burns - Brookfield CT
Hussein I. Hanafi - Goldens Bridge NY
Yuan Taur - Bedford NY
William C. Wille - Red Hood NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2976

US Classification:

257327

Abstract:

Metal oxide semiconductor field effect transistor (MOSFET) comprising a drain region and source region which enclose a channel region. A thin gate oxide is situated on the channel region and a gate conductor with vertical side walls is located on this gate oxide. The interfaces between the source region and channel region and the drain region and channel region are abrupt. Such an FET can be made using the following method: forming a dielectric stack on a semiconductor structure which at least comprises a pad oxide layer; defining an etch window having the lateral size and shape of a gate pillar to be formed; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the dielectric stack surrounding the gate hole; removing at least part of the dielectric stack such that a gate pillar with vertical side walls is set free.

Self-Aligned Diffused Source Vertical Transistors With Stack Capacitors In A 4F-Square Memory Cell Array

US Patent:

6077745, Jun 20, 2000

Filed:

Oct 29, 1997

Appl. No.:

8/960250

Inventors:

Stuart Mcallister Burns - Ridgefield CT
Hussein Ibrahim Hanafi - Goldens Bridge NY
Jeffrey J. Welser - Greenwich CT
Waldemar Walter Kocon - Wappingers Fall NY
Howard Leo Kalter - Colchester VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21336
H01L 218238

US Classification:

438270

Abstract:

A densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of adjacent bitlines may be isolated from each other without increasing the cell size and allowing a minimum area of approximately 4 F. sup. 2 to be maintained. The array is suitable for Gbit DRAM applications because the stack capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof.

4F-Square Memory Cell Having Vertical Floating-Gate Transistors With Self-Aligned Shallow Trench Isolation

US Patent:

5874760, Feb 23, 1999

Filed:

Jan 22, 1997

Appl. No.:

8/787419

Inventors:

Stuart Mcallister Burns - Ridgefield CT
Hussein Ibrahim Hanafi - Goldens Bridge NY
Jeffrey J. Welser - Greenwich CT
Waldemar Walter Kocon - Wappingers Fall NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29788

US Classification:

257315

Abstract:

A densely packed array of vertical semiconductor devices and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, acting as a channel, formed between source and drain regions. The source regions are self-aligned and located below the pillars. The source regions of adjacent bitlines are isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F. sup. 2 to be maintained. The isolated sources allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. The source may be initially implanted. Alternatively, the source may be diffused below the pillars after forming thereof.

Videos & Images

Youtube

Stuart Burns 3- Wood Simple Golf Swing

Duration:

12s

Category:

Sports

Description:

Stuart Burns young scottish golfer,recently turned professional. This is a slightly older golf swing but not much has changed tell me what you think. Seeking sponsorship for 2009 season.

Baker Street Cover Stuart Burns

Duration:

4m 37s

Category:

People & Blogs

Tom Hark (Piranhas Cover)- Stuart Burns

Duration:

2m 46s

Category:

Music

Ring Of Fire (Johnny Cash Cover) - Stuart Burns

Duration:

3m 7s

Category:

Music

Stuart Burns Wedge Shot

Duration:

14s

Category:

People & Blogs

Description:

Stuart Burns young Scottish golf professional wedge shot Narrowly missed the target at 85 yards... heartbreaking!

Sally Maclenanne (Pogues Cover) - Stuart Burns

Duration:

2m 38s

Category:

Music

Stuart Burns 6-Iron

Duration:

Category:

Sports

Description:

Stuart Burns Young Scottish golf professional Sorry about the camera angle I couldn't figure out how to rotate it.

Star Of The County Down Cover Stuart Burns

Duration:

2m 51s

Category:

People & Blogs

FAQ: Learn more about Stuart Burns

What is Stuart Burns's current residential address?

Stuart Burns's current known residential address is: 195 Summer Acres, Boone, NC 28607. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Stuart Burns?

Previous addresses associated with Stuart Burns include: 292 Hallowell Rd, Chelsea, ME 04330; 5803 Kayview, Austin, TX 78749; 3114 Sheldon Jackson, Anchorage, AK 99508; 14230 19Th, Phoenix, AZ 85023; 1228 90Th, Los Angeles, CA 90044. Remember that this information might not be complete or up-to-date.

Where does Stuart Burns live?

Boone, NC is the place where Stuart Burns currently lives.

How old is Stuart Burns?

Stuart Burns is 76 years old.

What is Stuart Burns date of birth?

Stuart Burns was born on 1947.

What is Stuart Burns's email?

Stuart Burns has such email addresses: stu.bu***@kone.com, burns***@hotmail.com, stuart.bu***@netzero.net, jburne***@adelphia.net, swar***@alltel.net, sfb***@yahoo.com. Note that the accuracy of these emails may vary and they are subject to privacy laws and restrictions.

What is Stuart Burns's telephone number?

Stuart Burns's known telephone numbers are: 410-778-6714, 417-286-3452, 503-436-2785, 602-368-2529, 703-934-4728, 817-605-8196. However, these numbers are subject to change and privacy restrictions.

How is Stuart Burns also known?

Stuart Burns is also known as: Stuart A Burns, Stewart S Burns, Stuart B Graham. These names can be aliases, nicknames, or other names they have used.

Who is Stuart Burns related to?

Known relatives of Stuart Burns are: Alyssa Smith, Bryan Smith, Graham Burns, Hannah Burns, Margaret Burns, Cherry Burns, Marlene Hannah. This information is based on available public records.

What are Stuart Burns's alternative names?

Known alternative names for Stuart Burns are: Alyssa Smith, Bryan Smith, Graham Burns, Hannah Burns, Margaret Burns, Cherry Burns, Marlene Hannah. These can be aliases, maiden names, or nicknames.

Name Variants	Stu Burns	Stew Burns
Ages	29 to 76
Phones	410-778-6714	417-286-3452	503-436-2785
Addresses	4204 Warren St, Davenport, IA 52806	292 Hallowell Rd, Chelsea, ME 04330	5803 Kayview, Austin, TX 78749
Business records	Owner and Graphic Designer / Duck Goose Printing	Assistant Commissioner, Public Buildings Service / Gsa	Director of Operations / Magnitude Life Sciences Llc

Stuart Burns

What do we know about Stuart Burns

Public information about Stuart Burns

Resumes

Resumes

Chief Of Staff

Senior Govt Relations Representative

General Secretary - Imm Usa

Vice President - Risk Analyst Iii

Real Estate Agent

Pilot

Stuart Burns

Food Service Worker

Phones & Addresses

Business Records

Publications

Us Patents

Reactive Ion Etch Loading Measurement Technique

2F-Square Memory Cell For Gigabit Memory Applications

Anisotropic Nitride Etch Process With High Selectivity To Oxide And Photoresist Layers In A Damascene Etch Scheme

Self-Aligned Diffused Source Vertical Transistors With Stack Capacitors In A 4F-Square Memory Cell Array

2F-Square Memory Cell For Gigabit Memory Applications

Field Effect Transistors With Vertical Gate Side Walls And Method For Making Such Transistors

Self-Aligned Diffused Source Vertical Transistors With Stack Capacitors In A 4F-Square Memory Cell Array

4F-Square Memory Cell Having Vertical Floating-Gate Transistors With Self-Aligned Shallow Trench Isolation

FAQ: Learn more about Stuart Burns

Possible Relatives