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Russell Houghton

In the United States, there are 50 individuals named Russell Houghton spread across 32 states, with the largest populations residing in California, Michigan, Iowa. These Russell Houghton range in age from 45 to 80 years old. Some potential relatives include Wayne Houghton, Betty Houghton, Aaron Houghton. You can reach Russell Houghton through various email addresses, including ghough***@att.net, rhough***@excite.com, brandonhough***@worldnet.att.net. The associated phone number is 541-788-2394, along with 6 other potential numbers in the area codes corresponding to 515, 830, 860. For a comprehensive view, you can access contact details, phone numbers, addresses, emails, social media profiles, arrest records, photos, videos, public records, business records, resumes, CVs, work history, and related names to ensure you have all the information you need.

Public information about Russell Houghton

Phones & Addresses

Name
Addresses
Phones
Russell J Houghton
717-338-1560
Russell J Houghton
802-879-7597
Russell M Houghton
559-243-9554
Russell M Houghton
559-442-1036
Russell M Houghton
231-775-8978
Russell R Houghton
207-833-6695
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Publications

Us Patents

Method For Novel Soi Dram Bicmos Npn

US Patent:
6492211, Dec 10, 2002
Filed:
Sep 7, 2000
Appl. No.:
09/656819
Inventors:
Ramachandra Divakaruni - Somers NY
Russell J. Houghton - Essex Junction VT
Jack A. Mandelman - Stormville NY
W. David Pricer - Charlotte VT
William R. Tonti - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2100
US Classification:
438155, 438234, 257349
Abstract:
There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PNP device is implemented by changing the array transistor to a PFET. Particularly, a BICMOS device is fabricated in SOI. The bipolar emitter contacts and CMOS diffusion contacts are formed simultaneously of polysilicon plugs. The CMOS diffusion contact is the plug contact from bitline to storage node of a memory cell.

Low Input Impedance Line/Bus Receiver

US Patent:
6498518, Dec 24, 2002
Filed:
Jul 14, 2000
Appl. No.:
09/617680
Inventors:
Russell J. Houghton - Essex Junction VT
Jack A. Mandelman - Stormville NY
Azzouz Nezar - Shillington PA
Wilbur D. Pricer - Charlotte VT
William R. Tonti - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 522
US Classification:
327 72, 327 74, 327 68, 327 77
Abstract:
A current sensing circuit connected to a power supply terminal and having at least one input terminal and at least one output terminal includes at least one bipolar transistor having a base, emitter and collector, at least one current mirror amplifier connected to the power supply terminal, the current mirror amplifier having an input connected to the collector and having at least one output connected to the emitter, and a DC voltage source connected to the base.

Low-Power Dc Voltage Generator System

US Patent:
6337595, Jan 8, 2002
Filed:
Jul 28, 2000
Appl. No.:
09/627599
Inventors:
Louis L. Hsu - Fishkill NY
Rajiv V. Joshi - Yorktown Heights NY
Russell J. Houghton - Essex Junction VT
Wayne F. Ellis - Jericho VT
Jeffrey H. Dreibelbis - Williston VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G05F 302
US Classification:
327538, 327540, 327530, 323314
Abstract:
A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e. g. , one volt to 1. 5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e. g. , from 1. 5 volts to about 2. 5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt. A one-volt negative voltage pump circuit is also included for pumping the voltages of at least one corresponding charge pump circuit, even when an operating voltage of the DC generator system is at or near one-volt. The DC voltage generator system is specifically designed to be implemented within battery-operated devices having at least one memory unit.

Low-Power Dc Voltage Generator System

US Patent:
6507237, Jan 14, 2003
Filed:
Jan 3, 2002
Appl. No.:
10/039874
Inventors:
Louis L. Hsu - Fishkill NY
Rajiv V. Joshi - Yorktown Heights NY
Russell J. Houghton - Essex Junction VT
Wayne F. Ellis - Jericho VT
Jeffrey H. Dreibelbis - Williston VT
Assignee:
IBM Corporation - Armonk NY
International Classification:
G05F 110
US Classification:
327538, 327536, 327537, 323313, 363 59
Abstract:
A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e. g. , one volt to 1. 5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e. g. , from 1. 5 volts to about 2. 5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt. A one-volt negative voltage pump circuit is also included for pumping the voltages of at least one corresponding charge pump circuit, even when an operating voltage of the DC generator system is at or near one-volt. The DC voltage generator system is specifically designed to be implemented within battery-operated devices having at least one memory unit.

Sense Amplifier Threshold Compensation

US Patent:
6518827, Feb 11, 2003
Filed:
Jul 27, 2001
Appl. No.:
09/917059
Inventors:
John A. Fifield - Underhill VT
Robert H. Dennard - New Rochelle NY
Russell J. Houghton - Essex Junction VT
Toshiaki Kirihara - Poughkeepsie NY
Wing Luk - Chappaqua NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 301
US Classification:
327534
Abstract:
A method and system are disclosed for adjusting the threshold in MOS devices, in particular for devices used in DRAM sense amplifiers. The effects of process and temperature variations on the threshold are compensated by a back-bias voltage. A comparison of an indicating voltage and a reference voltage is used to generate the back-bias voltage. The direction of back-bias voltage may be either in the backward, or in the forward bias direction.

Methods And Apparatus For Blowing And Sensing Antifuses

US Patent:
6346846, Feb 12, 2002
Filed:
Dec 17, 1999
Appl. No.:
09/466479
Inventors:
Claude L. Bertin - South Burlington VT
John A. Fifield - Underhill VT
Russell J. Houghton - Essex Junction VT
William R. Tonti - Essex Junction VT
Nicholas M. Van Heel - Burlington VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01H 3776
US Classification:
327525
Abstract:
Methods and apparatus for blowing and sensing antifuses are provided. Specifically, in a first aspect, a method is provided for changing the state of one of a plurality of antifuses by selecting one of the bank of antifuses and applying a high voltage to change the state of the selected antifuse. In second and third aspects, apparatus are provided for performing the method of the first aspect. In a fourth aspect, a method is provided for boosting a voltage that includes the steps of generating a first voltage within a first stage storage mechanism of a first stage voltage booster circuit, generating a second voltage equaling about twice the first voltage within a first and a second, second stage storage mechanism of a second stage voltage booster circuit, and generating about thrice the first voltage based on the second voltage of the second stage voltage booster circuit. In a fifth aspect, apparatus are provided for performing the method of the fourth aspect.

Low-Power Band-Gap Reference And Temperature Sensor Circuit

US Patent:
6531911, Mar 11, 2003
Filed:
Jul 7, 2000
Appl. No.:
09/611519
Inventors:
Louis L. Hsu - Fishkill NY
Rajiv V. Joshi - Yorktown Heights NY
Russell J. Houghton - Essex Junction VT
Assignee:
IBM Corporation - Armonk NY
International Classification:
H01L 3500
US Classification:
327512, 327539
Abstract:
A combined low-voltage, low-power band-gap reference and temperature sensor circuit is provided for providing a band-gap reference parameter and for sensing the temperature of a chip, such as an eDRAM memory unit or CPU chip, using the band-gap reference parameter. The combined sensor circuit is insensitive to supply voltage and a variation in the chip temperature. The power consumption of both circuits, i. e. , the band-gap reference and the temperature sensor circuits, encompassing the combined sensor circuit is less than one W. The combined sensor circuit can be used to monitor local or global chip temperature. The result can be used to (1) regulate DRAM array refresh cycle time, e. g. , the higher the temperature, the shorter the refresh cycle time, (2) to activate an on-chip or off-chip cooling or heating device to regulate the chip temperature, (3) to adjust internally generated voltage level, and (4) to adjust the CPU (or microprocessor) clock rate, i. e. , frequency, so that the chip will not overheat. The combined band-gap reference and temperature sensor circuit of the present invention can be implemented within battery-operated devices having at least one memory unit.

Method To Improve Charge Pump Reliability, Efficiency And Size

US Patent:
6570434, May 27, 2003
Filed:
Sep 15, 2000
Appl. No.:
09/662685
Inventors:
Louis Hsu - Fishkill NY
Russell J. Houghton - Essex Junction VT
Oliver Weinfurtner - Gilching, DE
Assignee:
Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY
International Classification:
G05F 302
US Classification:
327536
Abstract:
A dynamic clamp is used in conjunction with capacitors with thinner dielectric or with deep trench capacitors to solve the problem of dielectric breakdown in high stress capacitors. The dynamic clamp is realized using a two stage pump operation cycle such that, during a first stage pump cycle, a middle node of a pair of series connected capacitors is pre-charged to a supply voltage and, during a second stage pump cycle, the middle node is coupled by a boost clock. Thus, at any moment in the pump operation cycle, the voltage across the capacitors is held within a safety range.

FAQ: Learn more about Russell Houghton

How old is Russell Houghton?

Russell Houghton is 63 years old.

What is Russell Houghton date of birth?

Russell Houghton was born on 1960.

What is Russell Houghton's email?

Russell Houghton has such email addresses: ghough***@att.net, rhough***@excite.com, brandonhough***@worldnet.att.net, russell.hough***@gmail.com, iam_all4u***@hotmail.com, flowereli2***@yahoo.com. Note that the accuracy of these emails may vary and they are subject to privacy laws and restrictions.

What is Russell Houghton's telephone number?

Russell Houghton's known telephone numbers are: 541-788-2394, 515-371-1386, 830-998-7593, 860-651-0449, 515-961-7890, 515-962-0019. However, these numbers are subject to change and privacy restrictions.

Who is Russell Houghton related to?

Known relatives of Russell Houghton are: Elisha Swainston, Amy Morris, Candice Edwards, Jordan Houghton, Russell Houghton, Veronica Houghton, Jenny Dinehart. This information is based on available public records.

What are Russell Houghton's alternative names?

Known alternative names for Russell Houghton are: Elisha Swainston, Amy Morris, Candice Edwards, Jordan Houghton, Russell Houghton, Veronica Houghton, Jenny Dinehart. These can be aliases, maiden names, or nicknames.

What is Russell Houghton's current residential address?

Russell Houghton's current known residential address is: 205 S Lincoln St Apt C, Stanton, MI 48888. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Russell Houghton?

Previous addresses associated with Russell Houghton include: 940 Monroe Rd, Littleton, NH 03561; 61167 Dayspring Dr, Bend, OR 97702; 1800 S E Dr, Indianola, IA 50125; 314 4Th St, Murray, IA 50174; 35140 167Th St, Faulkton, SD 57438. Remember that this information might not be complete or up-to-date.

Where does Russell Houghton live?

Stanton, MI is the place where Russell Houghton currently lives.

How old is Russell Houghton?

Russell Houghton is 63 years old.

Russell Houghton from other States

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