Ian Melville

In the United States, there are 10 individuals named Ian Melville spread across 18 states, with the largest populations residing in Florida, New Mexico, Virginia.

Last updated Dec 29, 2023

Public information about Ian Melville

Phones & Addresses

Name

Addresses

Phones

Ian Melville

13224 122Nd Ave, Happy Valley, OR 97015

503-427-0455

Ian Melville

51 Cutter Ln, Tiverton, RI 02878

401-816-0346

Ian J Melville

5006 Harrington Ct, Tampa, FL 33624

813-969-1383

Ian Melville

Portland, OR

503-427-0455

Ian Melville

Tucson, AZ

520-721-9134

Ian K Melville

20 High Falls Rd, West Saugerties, NY 12477

845-246-8538

Ian Melville

West Saugerties, NY

845-246-8538

Ian Melville

4521 Riverwatch Dr, Bonita Springs, FL 34134

239-947-7092

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Publications

Us Patents

Semiconductor Chips With Crack Stop Regions For Reducing Crack Propagation From Chip Edges/Corners

US Patent:

7875502, Jan 25, 2011

Filed:

May 27, 2010

Appl. No.:

12/788521

Inventors:

Peter J. Brofman - Hopewell Junction NY, US
Jon Alfred Casey - Poughkeepsie NY, US
Ian D. Melville - Highland NY, US
David L. Questad - Hopewell Junction NY, US
Wolfgang Sauter - Richmond VT, US
Thomas Anthony Wassick - Lagrangeville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/78

US Classification:

438113, 257E23081

Abstract:

A chip fabrication method. A provided structure includes: a transistor on a semiconductor substrate, N interconnect layers on the semiconductor substrate and the transistor (N>0), and a first dielectric layer on the N interconnect layers. The transistor is electrically coupled to the N interconnect layers. P crack stop regions and Q crack stop regions are formed on the first dielectric layer (P, Q>0). The first dielectric layer is sandwiched between the N interconnect layers and a second dielectric layer that is formed on the first dielectric layer. Each P crack stop region is completely surrounded by the first and second dielectric layers. The second dielectric layer is sandwiched between the first dielectric layer and an underfill layer that is formed on the second dielectric layer. Each Q crack stop region is completely surrounded by the first dielectric layer and the underfill layer.

Method And Structure To Reduce Cracking In Flip Chip Underfill

US Patent:

7919356, Apr 5, 2011

Filed:

Jul 31, 2007

Appl. No.:

11/831026

Inventors:

Mukta G. Farooq - Hopewell Junction NY, US
Robert Hannon - Wappingers Falls NY, US
Dae-Young Jung - Vestal NY, US
Ian D. Melville - Highland NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438108, 438112, 438118, 438127

Abstract:

A method of assembling a microelectronic flip-chip arrangement includes attaching a chip having a defined length to a supporting substrate, wherein the chip forms a chip shadow line of the defined length on the supporting substrate, creating a first non-wettable zone on an outer portion of the bottom surface of the chip, creating a second non-wettable zone on a portion of the supporting substrate outside the chip shadow line, underfilling the chip and forming a fillet, wherein the fillet does not extend beyond the chip shadow line, and hardening the underfill including the fillet.

Method And Structure For Eliminating Aluminum Terminal Pad Material In Semiconductor Devices

US Patent:

7375021, May 20, 2008

Filed:

Apr 4, 2006

Appl. No.:

11/308539

Inventors:

Daniel C. Edelstein - White Plains NY, US
Mukta G. Farooq - Wappingers Falls NY, US
Robert Hannon - Wappingers Falls NY, US
Ian D. Melville - Highland NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438613, 257738, 257780, 257E21508

Abstract:

A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad in an upper level of a semiconductor wafer, forming an insulating stack over the terminal copper pad, and patterning and opening a terminal via within a portion of the insulating stack so as to leave a bottom cap layer of the insulating stack protecting the terminal copper pad. An organic passivation layer is formed and patterned over the top of the insulating stack, and the bottom cap layer over the terminal copper pad is removed. A ball limiting metallurgy (BLM) stack is deposited over the organic passivation layer and terminal copper pad, and a solder ball connection is formed on a patterned portion of the BLM stack.

Underbump Metallurgy For Enhanced Electromigration Resistance

US Patent:

8022543, Sep 20, 2011

Filed:

Mar 25, 2008

Appl. No.:

12/054713

Inventors:

Mukta G. Farooq - Hopewell Junction NY, US
Robert Hannon - Wappingers Falls NY, US
Emily R. Kinser - Poughkeepsie NY, US
Ian D. Melville - Highland NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48

US Classification:

257753, 257734, 257738, 257750

Abstract:

A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer, which provides a highly conductive structure that distributes current uniformly due to the higher electrical conductivity of the material than the layers above or below. A stack of the second metallic diffusion barrier layer and a wetting promotion layer is formed, on which a C4 ball is bonded. The elemental metal conductive layer distributes the current uniformly within the underbump metallurgy structure, which induces a more uniform current distribution in the C4 ball and enhanced electromigration resistance of the C4 ball.

Soft Error Rate Mitigation By Interconnect Structure

US Patent:

8120175, Feb 21, 2012

Filed:

Nov 30, 2007

Appl. No.:

11/947832

Inventors:

Mukta G. Farooq - Hopewell Junction NY, US
Ian D. Melville - Highland NY, US
Kevin S. Petrarca - Newburgh NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48

US Classification:

257737, 257703, 257E23115, 418614

Abstract:

A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.

Solder Connector Structure And Method

US Patent:

7470985, Dec 30, 2008

Filed:

Jul 31, 2006

Appl. No.:

11/461208

Inventors:

Mukta G. Farooq - Hopewell Junction NY, US
Laertis Economikos - Wappingers Falls NY, US
Ian D. Melville - Highland NY, US
Kevin S. Petrarca - Newburgh NY, US
Richard P. Volant - New Fairfield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48
H01L 23/52

US Classification:

257737, 257738

Abstract:

Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well.

Passivation Layer Surface Topography Modifications For Improved Integrity In Packaged Assemblies

US Patent:

8236615, Aug 7, 2012

Filed:

Nov 25, 2009

Appl. No.:

12/625590

Inventors:

Alexandre Blander - Bromont, CA
Jon A Casey - Poughkeepsie NY, US
Timothy H Daubenspeck - Colchester VT, US
Ian D Melville - Highland NY, US
Jennifer V Muncy - Ridgefield CT, US
Marie-Claude Paquet - Bromont, CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438118, 438127, 257788, 257E23132

Abstract:

A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic material and expose portions of such solids creates enhanced surface roughness, which provides a significant advantage with respect to adhesion of that passivation layer to the packaging underfill material.

Soft Error Rate Mitigation By Interconnect Structure

US Patent:

8445374, May 21, 2013

Filed:

Jan 30, 2012

Appl. No.:

13/361057

Inventors:

Mukta G. Farooq - Hopewell Junction NY, US
Ian D. Melville - Highland NY, US
Kevin S. Petrarca - Newburgh NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438613, 438614, 257737

Abstract:

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FAQ: Learn more about Ian Melville

What is Ian Melville's telephone number?

Ian Melville's known telephone numbers are: 520-336-7097, 563-285-5502, 617-450-9127, 520-721-9134, 813-969-1383, 845-246-8538. However, these numbers are subject to change and privacy restrictions.

How is Ian Melville also known?

Ian Melville is also known as: Ian James Melville, James I Melville. These names can be aliases, nicknames, or other names they have used.

Who is Ian Melville related to?

Known relatives of Ian Melville are: Hilary Melville, Hugh Melville, Jennifer Melville, Stuart Melville, Alan Melville, Janet Smith, Joy Spencer. This information is based on available public records.

What are Ian Melville's alternative names?

Known alternative names for Ian Melville are: Hilary Melville, Hugh Melville, Jennifer Melville, Stuart Melville, Alan Melville, Janet Smith, Joy Spencer. These can be aliases, maiden names, or nicknames.

What is Ian Melville's current residential address?

Ian Melville's current known residential address is: 2835 Hartwick, Tucson, AZ 85715. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Ian Melville?

Previous addresses associated with Ian Melville include: 9717 Camino Del Sol Ne, Albuquerque, NM 87111; 8889 Thornton Town Pl, Raleigh, NC 27616; 1105 Brown St, Bettendorf, IA 52722; 233 Sterling Pl, Highland, NY 12528; 64 Queensberry St, Boston, MA 02215. Remember that this information might not be complete or up-to-date.

Where does Ian Melville live?

Tucson, AZ is the place where Ian Melville currently lives.

How old is Ian Melville?

Ian Melville is 71 years old.

What is Ian Melville date of birth?

Ian Melville was born on 1953.

What is Ian Melville's email?

Ian Melville has such email addresses: imelvi***@sbcglobal.net, gdar***@hotmail.com, ianmelvi***@juno.com, nmelvi***@cs.com. Note that the accuracy of these emails may vary and they are subject to privacy laws and restrictions.

Possible Relatives

David Melville Dean Melville Dale Melville Deborah Melville Dan Melville Daniel Melville Denise Melville Ian Johnston Ian Stanford Ian White

Ages	22 to 71
Phones	520-336-7097	563-285-5502	617-450-9127
Addresses	9160 E Showcase Ln, Tucson, AZ 85749	9717 Camino Del Sol Ne, Albuquerque, NM 87111	8889 Thornton Town Pl, Raleigh, NC 27616
Business records	Process Engineer / Novozymes	Senior Engineering Manager / Ibm	Uplink engineer / Working for myself

Ian Melville

What do we know about Ian Melville

Public information about Ian Melville

Phones & Addresses

Publications

Us Patents

Semiconductor Chips With Crack Stop Regions For Reducing Crack Propagation From Chip Edges/Corners

Method And Structure To Reduce Cracking In Flip Chip Underfill

Method And Structure For Eliminating Aluminum Terminal Pad Material In Semiconductor Devices

Underbump Metallurgy For Enhanced Electromigration Resistance

Soft Error Rate Mitigation By Interconnect Structure

Solder Connector Structure And Method

Passivation Layer Surface Topography Modifications For Improved Integrity In Packaged Assemblies

Soft Error Rate Mitigation By Interconnect Structure

FAQ: Learn more about Ian Melville

Possible Relatives