Gary Hammond

6584558, Jun 24, 2003

Apr 24, 2002

10/132554

Gary Hammond - Campbell CA
Donald Alpert - Santa Clara CA
Kevin Kahn - Portland OR
Harsh Sharangpani - Santa Clara CA

Intel Corporation - Santa Clara CA

G06F 940

712244, 710269

An article representing a processor providing event handling functionality is described. According to one embodiment of the invention, the article includes a machine readable medium storing data representing a processor including an instruction set unit and an event handling unit, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second unit are to cause the article to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.

6584573, Jun 24, 2003

Aug 30, 1999

09/385204

Russ Wunderlich - Olympia WA
Yan Li - Olympia WA
Mani Ayyar - Cupertino CA
Gary N. Hammond - Fort Collins CO

Intel Corporation - Santa Clara CA

G06F 126

713322, 713323

A computer system enters or exits a sleeping state, such as the ACPI âS â state, in response to a sleep or wake event. Upon detecting the sleep or wake event, a system component generates a sleep or wake signal that instructs the computer to enter or exit the sleeping state. This sleep or wake signal is of a type to which the computers processor does not respond. Therefore, a PMI signal is asserted in response to the sleep or wake signal. The PMI signal, when asserted, causes the processor to halt program execution.

6393544, May 21, 2002

Oct 31, 1999

09/430793

William R. Bryg - Saratoga CA
Stephen G. Burger - Santa Clara CA
Gary N. Hammond - Fort Collins CO
James O. Hays - San Jose CA
Jerome C. Huck - Palo Alto CA
Jonathan K. Ross - Woodinville WA
Sunil Saxena - Sunnyvale CA
Koichi Yamada - San Jose CA

Institute for the Development of Emerging Architectures, L.L.C. - Cupertino CA

G06F 1200

711220, 711203, 711216, 711206, 711221, 711202

A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A âshort formatâ page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, and does not store tags or chain links. A single âlong formatâ page table is provided for the entire system, supports chained segments, and includes hash tag fields. The method of the present invention forms an entry address from a virtual address, with the entry address referencing an entry of the page table. To form the entry address, first a hash page number is formed from the virtual address by shifting the virtual address right based on the page size of the region of the virtual address. If the computer system is operating with long format page tables, the next step is to form a hash index by combining the hash page number and the region identifier referenced by the region portion of the virtual address, and to form a table offset by shifting the hash index left by K bits, wherein each long format page table entry is 2 bytes long. However, if the computer system is operating with short format page tables, the next step is to form a hash index by setting the hash index equal to the hash page number, and to form a table offset by shifting the hash index left by L bits, wherein each short format page table entry is 2 bytes long.

6604184, Aug 5, 2003

Jun 30, 1999

09/344267

Achmed R. Zahir - Menlo Park CA
Gary N. Hammond - Fort Collins CO
John H. Crawford - Saratoga CA

Intel Corporation - Santa Clara CA

G06F 1200

711207, 711209, 711219, 711220

The present invention is a method and apparatus to map virtual memory space. A region register file provides a region identifier for a virtual address in the virtual memory space. The virtual address includes a virtual region number and a virtual page number. A virtual page table look-up circuit is coupled to the region register file to generate a page table entry (PTE) virtual address from virtual address parameters. The virtual address parameters include the virtual address.

6625693, Sep 23, 2003

May 4, 1999

09/304372

Ken Arora - Cupertino CA
Harshvardhan Sharangpani - Santa Clara CA
Gary Hammond - Fort Collins CO

Intel Corporation - Santa Clara CA

G06F 1200

711125, 711140, 712244

Fast exception processing is disclosed. In one embodiment, a system includes a splice cache, an exception logic, and an instrumentation mechanism. The splice cache contains one or more lightweight handlers. The exception logic is coupled to the splice cache and determines whether the corresponding lightweight handler for an exception is located in the splice cache. The instrumentation mechanism is coupled to the splice cache. The instrumentation mechanism inserts the lightweight handler into an execution stream.

6397301, May 28, 2002

Dec 29, 1999

09/473973

Nhon T. Quach - San Jose CA
Gary Hammond - Campbell CA
Kin-Yip Liu - Santa Clara CA

Intel Corporation - Santa Clara CA

G06F 1200

711138, 711163

Information in a cache that is coupled to a processor is secured by recording the location in the cache of information that is being secured, and performing a cache avoidance procedure instead of allowing the instruction to access the area of the cache containing the information being secured.

6711653, Mar 23, 2004

Mar 30, 2000

09/539196

Nhon Quach - San Jose CA
Gary N. Hammond - Fort Collins CO

Intel Corporation - Santa Clara CA

G06F 1200

711146, 711143, 711207, 711145, 713 1

The present invention provides a computer system that is capable of operating in a first or second cache coherency mode according to the operating environment in which the computer system is booted to run. If the operating environment supports memory attribute aliasing (MAA), the computer system implements a cache coherency mechanism that supports MAA. If the operating environment does not support MAA, the computer system implements a cache coherency mechanism that does not support MAA.

7062636, Jun 13, 2006

Sep 19, 2002

10/247894

Jeffery J. Baxter - Los Gatos CA, US
Gary N. Hammond - Fort Collins CO, US
Nazar A. Zaidi - San Jose CA, US

Intel Corporation - Santa Clara CA

G06F 9/38

712218, 711141, 712 23, 712216

Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may be many clock cycles away from the issue engine The issue engine categorizes operations as at least one of either a speculative operation, which perform computations, or an architectural operation, which has potential to fault or cause an exception. Potentially excepting operations may be decomposed into two separate micro-operations: a speculative micro-operation, which is used to generate data results speculatively so that operations dependent on the results may be speculatively issued, and an architectural micro-operation, which signals the faulting condition for the excepting operation. A STORE operation becomes an architectural operation and all previous faulting conditions may be guaranteed to have evaluated before a STORE is issued.