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Daniel Maynard

In the United States, there are 484 individuals named Daniel Maynard spread across 49 states, with the largest populations residing in Florida, Ohio, California. These Daniel Maynard range in age from 35 to 74 years old. Some potential relatives include Kaylin Bean, Ray Hansen, Michael Hansen. You can reach Daniel Maynard through various email addresses, including tmayn***@charter.net, fmayn***@msn.com, grapesc***@yahoo.com. The associated phone number is 614-877-2180, along with 6 other potential numbers in the area codes corresponding to 520, 606, 810. For a comprehensive view, you can access contact details, phone numbers, addresses, emails, social media profiles, arrest records, photos, videos, public records, business records, resumes, CVs, work history, and related names to ensure you have all the information you need.

Public information about Daniel Maynard

Resumes

Resumes

Daniel Maynard

Daniel Maynard Photo 1
Location:
Greater New York City Area
Industry:
Real Estate

Sales Associate At Origins Real Estate

Daniel Maynard Photo 2
Position:
Sales Associate at Origins Real Estate
Location:
Greater Atlanta Area
Industry:
Real Estate
Work:
Origins Real Estate
Sales Associate

Medical Records Clerk At Friends Hospital

Daniel Maynard Photo 3
Position:
Medical Records Clerk at Friends Hospital
Location:
Greater Philadelphia Area
Industry:
Hospital & Health Care
Work:
Friends Hospital - Greater Philadelphia Area since Apr 2010
Medical Records Clerk Law Offices of Stewart Crawford Sep 2009 - Dec 2009
Special Counsel Paralegal Texas Department of Family and Protective Services Nov 2008 - Jan 2009
CPS Investigation Specialist II National Society for American Indian Elderly Jul 2007 - Jul 2008
VISTA(Volunteer in Service to America)
Education:
Temple University 2012 - 2014
Master's degree, Health Informatics Villanova University 2009 - 2009
Paralegal Certificate, ABA; Post Baccalaureate Program Temple University 2003 - 2007
Bachelor of Arts, Psychology
Skills:
Community Outreach, Interviews
Interests:
Reading, basketball, lifting weights

Financial Services Professional

Daniel Maynard Photo 4
Location:
Greater Denver Area
Industry:
Financial Services

Daniel Maynard

Daniel Maynard Photo 5
Location:
Greater Atlanta Area
Industry:
Insurance

President At Connecture

Daniel Maynard Photo 6
Position:
President at Connecture, Inc., Strategic Advisor at GrandCare Systems, Member of Board of Directors at Hayes Technology Group, Inc.
Location:
Greater Milwaukee Area
Industry:
Computer Software
Work:
Connecture, Inc. since 2012
President GrandCare Systems - West Bend, WI since Feb 2013
Strategic Advisor Hayes Technology Group, Inc. - Vernon Hills, IL since 2012
Member of Board of Directors
Education:
University of Wisconsin-Milwaukee - School of Business Administration 1985 - 1988
Skills:
Corporate Development, Organizational Development, Cultural Development, Software Development, Software Delivery Operations, Financial Management, Enterprise Software Sales, Marketing Development, Business Development, Product Management, Strategy Setting, Healthcare Information Technology, Business Strategy, Technology Utilization

Daniel Maynard - Orlando, FL

Daniel Maynard Photo 7
Work:
Stay-At-Home Dad 2010 to 2000
Homemaker MedCorp Ambulance Service - Bucyrus, OH 2008 to 2010
EMT-Basic United States Marine Corp 2000 to 2008
Rifleman/Welder/Welding office management Nacarato Volvo - Nashville, TN 1997 to 2000
Parts Sales/Parts office management

Daniel Maynard - Hazel Green, AL

Daniel Maynard Photo 8
Work:
Jtl lawncare - Madison, WI Mar 2014 to Aug 2014
lawn care leader lockes automotive - Hazel Green, AL Sep 2012 to Jun 2014
Auto mechanic cinram - Huntsville, AL Apr 2009 to Apr 2012
line lead walmart - Huntsville, AL Aug 2005 to May 2009
stocker
Background search with BeenVerified
Data provided by Veripages

Phones & Addresses

Name
Addresses
Phones
Daniel T. Maynard
304-529-3754
Daniel B. Maynard, Jr
302-368-8020
Daniel J. Maynard
614-877-2180
Daniel Maynard, Sr
419-599-5296
Daniel A Maynard
317-758-4834
Daniel L. Maynard
520-749-3521

Business Records

Name / Title
Company / Classification
Phones & Addresses
Daniel A. Maynard
President, Owner
MAYNARD CONSTRUCTION BUILDER REMODELER CONTRACTOR, INC
Single-Family House Construction · Home Builders · Decks
163 N Ave, Attleboro, MA 02703
508-226-4591
Daniel Maynard
Owner
Dan's Roofing & Repair
Roofing
457 W Bellevue Hwy, Olivet, MI 49076
517-543-2803
Mr. Daniel Maynard
Owner
Dan's Roofing & Repair
Roofing Contractors
457 W Bellevue Hwy, Olivet, MI 49076
517-543-2803
Daniel Maynard
Owner
DM Enterprises
Computers-Dealers
3718 E Abercrombie Cir, Chattanooga, TN 37415
423-875-0421
Daniel L. Maynard
Owner
Maynard Trucking LLC
Local Trucking Operator
111 Front St, Kearney, NE 68845
Mr. Daniel Maynard
Esquire
Maynard & Associates, Attorneys at Law LLC
Attorneys & Lawyers
246 W Liberty St, Medina, OH 44256
330-725-2116
Daniel P. Maynard
President
3D Auto Works Inc
Automotive Engine Repair Service
1 Industrial Dr, Hudson, NH 03051
603-882-3400
Daniel J Maynard
President
JDA SOFTWARE, INC
14400 N 87 St, Scottsdale, AZ
12995 E Cibola Rd, Scottsdale, AZ

Publications

Us Patents

Ic Design Modeling Allowing Dimension-Dependent Rule Checking

US Patent:
7404164, Jul 22, 2008
Filed:
Feb 4, 2004
Appl. No.:
10/708039
Inventors:
Evanthia Papadopoulou - New York NY, US
Daniel N. Maynard - Craftsbury Common VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 7, 716 1
Abstract:
A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e. g. , numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e. g. , relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.

Method For Generating A Set Of Test Patterns For An Optical Proximity Correction Algorithm

US Patent:
7404174, Jul 22, 2008
Filed:
Jul 27, 2004
Appl. No.:
10/710648
Inventors:
David L. DeMaris - Austin TX, US
Mark A. Lavin - Katonah NY, US
William C. Leipold - Enosburg Falls VT, US
Daniel N. Maynard - Craftsbury Common VT, US
Maharaj Mukherjee - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 21, 716 18
Abstract:
A method of synthesizing layout patterns to test an optical proximity correction algorithm. The method comprises the steps of: embodying Walsh patterns in a set of Walsh pattern matrices; processing groups of matrices from the set of Walsh pattern matrices to form a set of test matrices; mapping the set of test matrices to a test pattern set.

Trench Isolation For Active Areas And First Level Conductors

US Patent:
6394638, May 28, 2002
Filed:
Apr 28, 2000
Appl. No.:
09/560212
Inventors:
Edward W. Sengle - Hinesburg VT
Mark D. Jaffe - Colchester VT
Daniel Nelson Maynard - Craftsbury Common VT
Mark Alan Lavin - Katonah NY
Eric Jeffrey White - North Farrisburg VT
John A. Bracchitta - So. Burlington VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21762
US Classification:
364491, 438129, 438400, 438424, 438439
Abstract:
A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.

System For Search And Analysis Of Systematic Defects In Integrated Circuits

US Patent:
7415695, Aug 19, 2008
Filed:
May 15, 2007
Appl. No.:
11/748575
Inventors:
Bette L. Bergman Reuter - Essex Junction VT, US
David L. DeMaris - Austin TX, US
Mark A. Lavin - Katonah NY, US
William C. Leipold - Enosburg Falls VT, US
Daniel N. Maynard - Craftsbury Common VT, US
Maharaj Mukherjee - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 21, 716 19
Abstract:
Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region.

Ic Layout Optimization To Improve Yield

US Patent:
7503020, Mar 10, 2009
Filed:
Jun 19, 2006
Appl. No.:
11/424922
Inventors:
Robert J. Allen - Jericho VT, US
Faye D. Baker - Burlington VT, US
Albert M. Chu - Essex VT, US
Michael S. Gray - Fairfax VT, US
Jason Hibbeler - Williston VT, US
Daniel N. Maynard - Craftsbury Common VT, US
Mervyn Y. Tan - Milton VT, US
Robert F. Walker - St. George VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 2, 716 5
Abstract:
A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i. e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

Method For Prediction Random Defect Yields Of Integrated Circuits With Accuracy And Computation Time Controls

US Patent:
6738954, May 18, 2004
Filed:
Aug 10, 2000
Appl. No.:
09/636478
Inventors:
Archibald J. Allen - Grand Isle VT
Wilm E. Donath - New York NY
Alan D. Dziedzic - Newburgh NY
Mark A. Lavin - Katonah NY
Daniel N. Maynard - Craftsbury Common VT
Dennis M. Newns - Yorktown Heights NY
Gustavo E. Tellez - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
716 4, 716 1
Abstract:
A method of computing a manufacturing yield of an integrated circuit having device shapes includes sub-dividing the integrated circuit into failure mechanism subdivisions (each of the failure mechanism subdivisions includes one or more failure mechanism and each of the failure mechanisms includes one or more defect mechanisms), partitioning the failure mechanism subdivisions by area into partitions, pre-processing the device shapes in each partition, computing an initial average number of faults for each of the failure mechanisms and for each partition by numerical integration of an average probability of failure of each failure mechanism, (the numerical integration produces a list of defect sizes for each defect mechanism, and the computing of the initial average includes setting a maximum integration error limit, a maximum sample size for a population of each defect size, and a maximum number of allowable faults for each failure mechansim), and computing a final average number of faults for the integrated circuit by iterativelly reducing a statistical error of the initial average number of faults for each of the failure mechanisms until the statistical error is below an error limit.

System For Search And Analysis Of Systematic Defects In Integrated Circuits

US Patent:
7552417, Jun 23, 2009
Filed:
Jun 4, 2008
Appl. No.:
12/132710
Inventors:
Bette L. Bergman Reuter - Essex Junction VT, US
David L. DeMaris - Austin TX, US
Mark A. Lavin - Katonah NY, US
William C. Leipold - Enosburg Falls VT, US
Daniel N. Maynard - Craftsbury Common VT, US
Maharaj Mukherjee - Wappingers Falls VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 21, 716 4, 716 5, 716 19
Abstract:
Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region.

Ic Design Modeling Allowing Dimension-Dependent Rule Checking

US Patent:
7555735, Jun 30, 2009
Filed:
Oct 29, 2007
Appl. No.:
11/926289
Inventors:
Evanthia Papadopoulou - New York NY, US
Daniel N. Maynard - Craftsbury Common VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 1, 716 5
Abstract:
A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e. g. , numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e. g. , relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.

FAQ: Learn more about Daniel Maynard

How old is Daniel Maynard?

Daniel Maynard is 74 years old.

What is Daniel Maynard date of birth?

Daniel Maynard was born on 1950.

What is Daniel Maynard's email?

Daniel Maynard has such email addresses: tmayn***@charter.net, fmayn***@msn.com, grapesc***@yahoo.com, damay***@ticon.net, broknd***@aol.com, dmaynar***@comcast.net. Note that the accuracy of these emails may vary and they are subject to privacy laws and restrictions.

What is Daniel Maynard's telephone number?

Daniel Maynard's known telephone numbers are: 614-877-2180, 520-749-3521, 606-836-6542, 810-659-6994, 317-758-4834, 337-783-2779. However, these numbers are subject to change and privacy restrictions.

How is Daniel Maynard also known?

Daniel Maynard is also known as: Daniel L Maynard, Dan Maynard, Daniela Maynard, Brian Maynard, Daniel Mmaynard. These names can be aliases, nicknames, or other names they have used.

Who is Daniel Maynard related to?

Known relatives of Daniel Maynard are: Martha Maynard, Paulette Maynard, Brian Maynard, Christine Maynard, Meredith Jacobson, Anthony Jacobson, Cindy Jacobson. This information is based on available public records.

What are Daniel Maynard's alternative names?

Known alternative names for Daniel Maynard are: Martha Maynard, Paulette Maynard, Brian Maynard, Christine Maynard, Meredith Jacobson, Anthony Jacobson, Cindy Jacobson. These can be aliases, maiden names, or nicknames.

What is Daniel Maynard's current residential address?

Daniel Maynard's current known residential address is: 104 Forest Dr, Eureka, MO 63025. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Daniel Maynard?

Previous addresses associated with Daniel Maynard include: 14 Holman St, Attleboro, MA 02703; 159 North Ave, Attleboro, MA 02703; 159 North Ave, Attleboro Falls, MA 02763; 163 North Ave, Attleboro, MA 02703; 21 Holman St, Attleboro, MA 02703. Remember that this information might not be complete or up-to-date.

Where does Daniel Maynard live?

Eureka, MO is the place where Daniel Maynard currently lives.

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