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Ayan Kar

In the United States, there are 8 individuals named Ayan Kar spread across 7 states, with the largest populations residing in California, Alabama, Georgia. These Ayan Kar range in age from 39 to 48 years old. Some potential relatives include Rikia Mcdaniel, Melanie Lehman, Shane Hattaway. For a comprehensive view, you can access contact details, phone numbers, addresses, emails, social media profiles, arrest records, photos, videos, public records, business records, resumes, CVs, work history, and related names to ensure you have all the information you need.
Last updated Jan 13, 2024
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Ayan Kar , Age 48
Dawsonville, GA
Has lived in:
Dawsonville, GA
Fultondale, AL
Tucker, GA
Atlanta, GA
Related to:
Samuel Mcdaniel
Angela Mcdaniel, 46
Carl Welch, 82
Rasselas Brown, 49
PhoneAddress
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Ayan Kar , Age 41
Portland, OR
Has lived in:
Portland, OR
Hillsboro, OR
State College, PA
Downers Grove, IL
PhoneAddress
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Ayan Kar , Age 39
Mission Viejo, CA
Has lived in:
Mission Viejo, CA
Los Angeles, CA
Long Beach, CA
Related to:
Eyan Kar
PhoneAddress
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Ayan Kar 
Long Beach, CA
Has lived in:
Long Beach, CA
PhoneAddress
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Ayan Kar 
Arlington, VA
Has lived in:
Arlington, VA
PhoneAddress
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Ayan Kar 
Sunnyvale, CA
Has lived in:
Sunnyvale, CA
PhoneAddress
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Ayan Kar 
Sylacauga, AL
Has lived in:
Sylacauga, AL
PhoneAddress
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Ayan Kar 
Dawsonville, GA
Has lived in:
Dawsonville, GA
PhoneAddress
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Public information about Ayan Kar

Resumes

Resumes

Owner

Ayan Kar Photo 1
Location:
720 Woodlawn Ave, Sylacauga, AL 35150
Industry:
Restaurants
Work:
Quiznos Sub
Owner

Ayan Kar

Ayan Kar Photo 2
Location:
Chicago, IL
Industry:
Electrical/Electronic Manufacturing
Education:
University of Illinois at Chicago 2006 - 2012
Skills:
Semiconductor Device

Graduate Student & Tutor At California State University, Long Beach

Ayan Kar Photo 3
Location:
Greater Los Angeles Area
Industry:
Computer Software

Ayan Kar - Long Beach, CA

Ayan Kar Photo 4
Work:
Student Services Division, Information Technology (CSULB) Aug 2012 to 2000
Student Assistant - Mobile App Developer (Volunteer position) Learning Assistance Center at CSULB Jan 2011 to 2000
Tutor Digicaptions India Pvt. Ltd - Bangalore, Karnataka Mar 2010 to May 2010
DVD Quality Assurance Engineer MeritTrac Services India Pvt. Ltd - Bangalore, Karnataka Aug 2007 to Apr 2009
Test Developer
Education:
California State University - Long Beach, CA 2010 to 2013
Master of Science in Computer Science Visvesvaraya Technological University - Bangalore, Karnataka Jan 2003 to Jan 2007
Bachelor of Engineering in Electronics & Communication Engineering
Skills:
C, C++, C#, VB.Net, VB6, Windows Phone, x86 Assembly Language, Windows, Silverlight, UI Design, Distributed computing, Linux, SQL, DSP, ASP.Net, XML, Web services/WCF, XAML, HTML, Flash, AJAX, Android, Mac OS X, Prototyping, Requirement gathering.

Lead Software Engineer

Ayan Kar Photo 5
Location:
Los Angeles, CA
Industry:
Computer Software
Work:
Headspace
Lead Software Engineer Gogii, Inc. Jun 2013 - Mar 2016
Software Engineer California State University, Long Beach Aug 2012 - May 2013
Student Assistant - Mobile App Developer Associated Students, Incorporated at California State University Long Beach Jan 2011 - May 2013
Tutor Digicaptions India Pvt Ltd Mar 2010 - May 2010
Dvd Quality Assurance Engineer Merittrac Service's Pvt Ltd. Aug 2007 - Apr 2009
Test Developer Windows Computer Store Dec 2001 - Dec 2002
Sales Associate
Education:
California State University, Long Beach 2010 - 2013
Master of Science, Masters B.m.s. Institute of Technology 2003 - 2007
Bachelor of Engineering, Bachelors Indian School Muscat 1999 - 2003
Skills:
Core Java, .Net, Distributed Systems, Git, Threads, Linux, Xaml, Google Api, C, Silverlight, Windows, Windows Phone, Mac Os X, Visual Studio, Ant, Visual Basic 5.0/6.0, Jenkins, Agile Methodologies, Json, Requirement Solicitation, Scrum, Android Development, Ajax, Asp.net, Project Documentation, Html, Mobile Applications, Programming, Java, Xml, Android, Testing, Web Services, Parallel Programming, Javascript, C++, Wcf, Dsp, Software Engineering, Sql, Test Driven Development, X86 Assembly, Software Development, Vb.net, C#, User Experience Design, Object Oriented Design, Flash, Databases

Component Design Engineer

Ayan Kar Photo 6
Location:
3924 northwest Tustin Ranch Dr, Portland, OR 97229
Industry:
Semiconductors
Work:
Intel Corporation May 2013 - May 2018
Ptd Device Engineer Intel Corporation May 2013 - May 2018
Component Design Engineer Penn State University Feb 2012 - Apr 2013
Postdoctoral Research Fellow Argonne National Laboratory Oct 2010 - Apr 2011
Graduate Research Associate University of Illinois at Chicago Aug 2006 - Jan 2011
Phd Los Alamos National Laboratory May 2010 - Aug 2010
Summer Intern Nasa Aug 2009 - Dec 2009
Graduate Researcher Argonne National Laboratory May 2009 - Jul 2009
Graduate Researcher Centre For Nanotechnology and Quantum Physics Jadavpur University Jun 2004 - May 2006
Research Scholar Indian Oil Corporation Limited May 2004 - Aug 2004
Summer Intern
Education:
University of Illinois at Chicago 2006 - 2012
Doctorates, Doctor of Philosophy, Engineering
Skills:
Characterization, Nanotechnology, Semiconductors, Cvd, Spectroscopy, Sensors, Thin Films, Photolithography, Scanning Electron Microscopy, Silicon, Optoelectronics, Nanomaterials, R&D, Surface, Afm, Materials, Microfabrication, Xps, Tem, Sputtering, Mems, Pvd
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Publications

Us Patents

Lateral Diodes In Stacked Transistor Technologies

US Patent:
2023008, Mar 23, 2023
Filed:
Sep 22, 2021
Appl. No.:
17/448384
Inventors:
- Santa Clara CA, US
Ayan Kar - Portland OR, US
Benjamin Orr - Beaverton OR, US
Kalyan C. Kolluru - Portland OR, US
Nathan D. Jack - Forest Grove OR, US
Patrick Morrow - Portland OR, US
Cheng-Ying Huang - Hillsboro OR, US
Charles C. Kuo - Hillsboro OR, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
H01L 27/02
H01L 27/092
H01L 29/06
H01L 29/417
H01L 29/423
H01L 29/786
H01L 21/02
H01L 29/66
H01L 21/8238
Abstract:
Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction path.

Novel Esd Protection Decoupled From Diffusion

US Patent:
2022019, Jun 23, 2022
Filed:
Dec 23, 2020
Appl. No.:
17/133595
Inventors:
- Santa Clara CA, US
Abhishek A. SHARMA - Portland OR, US
Charles C. KUO - Union City CA, US
Benjamin ORR - Portland OR, US
Nicholas THOMSON - Hillsboro OR, US
Ayan KAR - Portland OR, US
Arnab SEN GUPTA - Hillsboro OR, US
Kaan OGUZ - Beaverton OR, US
Brian S. DOYLE - Portland OR, US
Prashant MAJHI - San Jose CA, US
Van H. LE - Portland OR, US
Elijah V. KARPOV - Portland OR, US
International Classification:
H01L 27/02
H02H 9/04
Abstract:
Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.

Finfet Varactor Quality Factor Improvement

US Patent:
2020010, Apr 2, 2020
Filed:
Sep 28, 2018
Appl. No.:
16/147205
Inventors:
- Santa Clara CA, US
Mark ARMSTRONG - Portland OR, US
Saurabh MORARKA - Hillsboro OR, US
Carlos NIEVA-LOZANO - Beaverton OR, US
Ayan KAR - Portland OR, US
International Classification:
H01L 27/08
H01L 29/93
H01L 29/66
H01L 27/105
Abstract:
An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.

Substrate-Less Nanowire-Based Lateral Diode Integrated Circuit Structures

US Patent:
2022041, Dec 29, 2022
Filed:
Jun 24, 2021
Appl. No.:
17/357767
Inventors:
- Santa Clara CA, US
Kalyan KOLLURU - Portland OR, US
Ayan KAR - Portland OR, US
Rui MA - Portland OR, US
Benjamin ORR - Portland OR, US
Nathan JACK - Forest Grove OR, US
Biswajeet GUHA - Hillsboro OR, US
Brian GREENE - Portland OR, US
Lin HU - Portland OR, US
Chung-Hsun LIN - Portland OR, US
Sabih OMAR - Hillsboro OR, US
International Classification:
H01L 29/06
H01L 29/423
H01L 27/12
Abstract:
Substrate-less nanowire-based lateral diode integrated circuit structures, and methods of fabricating substrate-less nanowire-based lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a stack of nanowires. A plurality of P-type epitaxial structures is over the stack of nanowires. A plurality of N-type epitaxial structures is over the stack of nanowires. One or more gate structures is over the stack of nanowires. A semiconductor material is between and in contact with vertically adjacent ones of the stack of nanowires.

Substrate-Less Finfet Diode Architectures With Backside Metal Contact And Subfin Regions

US Patent:
2020040, Dec 24, 2020
Filed:
Jun 20, 2019
Appl. No.:
16/447874
Inventors:
- Santa Clara CA, US
Ayan KAR - Portland OR, US
Kalyan KOLLURU - Portland OR, US
Nathan JACK - Forest Grove OR, US
Rui MA - Portland OR, US
Mark BOHR - Aloha OR, US
Rishabh MEHANDRU - Portland OR, US
Halady Arpit RAO - Hillsboro OR, US
International Classification:
H01L 27/12
H01L 27/02
H01L 29/861
H01L 21/84
Abstract:
Embodiments include diode devices and transistor devices. A diode device includes a first fin region over a first conductive region and an insulator region, and a second fin region over a second conductive and insulator regions, where the second fin region is laterally adjacent to the first fin region, and the insulator region is between the first and second conductive regions. The diode device includes a first conductive via on the first conductive region, where the first conductive via is vertically adjacent to the first fin region, and a second conductive via on the second conductive region, where the second conductive via is vertically adjacent to the second fin region. The diode device may include conductive contacts, first portions on the first fin region, second portions on the second fin region, and gate electrodes between the first and second portions and the conductive contacts.

Vertical Diodes In Stacked Transistor Technologies

US Patent:
2023008, Mar 23, 2023
Filed:
Sep 22, 2021
Appl. No.:
17/448373
Inventors:
- Santa Clara CA, US
Nicholas A. Thomson - Hillsboro OR, US
Ayan Kar - Portland OR, US
Nathan D. Jack - Forest Grove OR, US
Kalyan C. Kolluru - Portland OR, US
Patrick Morrow - Portland OR, US
Cheng-Ying Huang - Hillsboro OR, US
Charles C. Kuo - Hillsboro OR, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
H01L 27/06
H01L 27/092
H01L 29/66
H01L 21/8238
Abstract:
Integrated circuits including vertical diodes. In an example, a first transistor is above a second transistor. The first transistor includes a first semiconductor body extending laterally from a first source or drain region. The first source or drain region includes one of a p-type dopant or an n-type dopant. The second transistor includes a second semiconductor body extending laterally from a second source or drain region. The second source or drain region includes the other of the p-type dopant or the n-type dopant. The first source or drain region and second source or drain region are at least part of a diode structure, which may have a PN junction (e.g., first and second source/drain regions are merged) or a PIN junction (e.g., first and second source/drain regions are separated by an intrinsic semiconductor layer, or a dielectric layer and the first and second semiconductor bodies are part of the junction).

Lateral Diodes In Stacked Transistor Technologies

US Patent:
2023008, Mar 23, 2023
Filed:
Sep 22, 2021
Appl. No.:
17/448385
Inventors:
- Santa Clara CA, US
Ayan Kar - Portland OR, US
Benjamin Orr - Beaverton OR, US
Kalyan C. Kolluru - Portland OR, US
Nathan D. Jack - Forest Grove OR, US
Patrick Morrow - Portland OR, US
Cheng-Ying Huang - Hillsboro OR, US
Charles C. Kuo - Hillsboro OR, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
H01L 27/02
H01L 27/092
H01L 29/06
H01L 29/417
H01L 29/423
H01L 29/786
H01L 21/02
H01L 29/66
H01L 21/8238
Abstract:
Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction paths.

FAQ: Learn more about Ayan Kar

Who is Ayan Kar related to?

Known relatives of Ayan Kar are: Melanie Lehman, Rikia Mcdaniel, Samuel Mcdaniel, Angela Mcdaniel, Carl Welch, Rasselas Brown, Shane Hattaway. This information is based on available public records.

What is Ayan Kar's current residential address?

Ayan Kar's current known residential address is: 3924 Nw Tustin Ranch Dr, Portland, OR 97229. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Ayan Kar?

Previous addresses associated with Ayan Kar include: 3515 Pleasantdale Rd, Atlanta, GA 30340; 1145 Taylor, Chicago, IL 60607. Remember that this information might not be complete or up-to-date.

Where does Ayan Kar live?

Dawsonville, GA is the place where Ayan Kar currently lives.

How old is Ayan Kar?

Ayan Kar is 48 years old.

What is Ayan Kar date of birth?

Ayan Kar was born on 1975.

Who is Ayan Kar related to?

Known relatives of Ayan Kar are: Melanie Lehman, Rikia Mcdaniel, Samuel Mcdaniel, Angela Mcdaniel, Carl Welch, Rasselas Brown, Shane Hattaway. This information is based on available public records.

Possible Relatives

David Kar A Kar Dawn Kar Debbie Kar Dave Kar Donna Kar Dorothy Kar Ayan Jones Ayan Mack Ayan Williams Ayan Mohamed Ayan Mohammed Ayan Nor Ayan Osman

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