Login about (844) 217-0978
FOUND IN STATES

Amit Sanghani

In the United States, there are 3 individuals named Amit Sanghani spread across 4 states, with the largest populations residing in California, Michigan, Ohio. These Amit Sanghani range in age from 49 to 52 years old. A potential relative includes Kavita Sanghavi. You can reach Amit Sanghani through their email address, which is asangh***@aol.com. The associated phone number is 408-223-2648, including 2 other potential numbers within the area code of 949. For a comprehensive view, you can access contact details, phone numbers, addresses, emails, social media profiles, arrest records, photos, videos, public records, business records, resumes, CVs, work history, and related names to ensure you have all the information you need.
Last updated 2023-12-29
Sponsored by TruthFinder
Amit D Sanghani , 52
San Jose, CA
Also known as:
Amit Dinesh Sanghani
Dinesh P Sanghani
Armit D Sanghani
Amit Samghani
Has lived in:
San Jose, CA
Campbell, CA
Sacramento, CA
College Station, TX
PhoneAddress
view full profile
Amit Y Sanghavi , 49
Sylvania, OH
Also known as:
Amit I
Amit Y Sanghani
Has lived in:
Sylvania, OH
Toledo, OH
Holland, OH
Lucas, OH
Related to:
Kavita Sanghavi
PhoneAddress
view full profile
Sponsored by TruthFinder
Dinesh P Sanghani 
Rancho Santa Margarita, CA
Also known as:
Amit Dinesh Sanghani
Amit D Sanghani
Has lived in:
Rancho Santa Margarita, CA
San Jose, CA
Folsom, CA
Campbell, CA
Related to:
Deval Sanghani, 48
Nayna Sanghani, 71
Smita Sanghani
Aruna Sanghani
Phone number:
408-223-****
PhoneAddress
view full profile

Public information about Amit Sanghani

Phones & Addresses

Name
Addresses
Phones
Amit D Sanghani
3104 Main St, Santa Ana, CA 92707
Amit D Sanghani
397 Giotto, Irvine, CA 92614
Amit D Sanghani
4901 Portmarnoch Ct, San Jose, CA 95138
408-223-2648
Amit D Sanghani
4110 College Ave, Bryan, TX 77801
Amit D Sanghani
255 Union Ave, Campbell, CA 95008
408-559-1621
Amit D Sanghani
392 Castlemaine Ct, San Jose, CA 95136
408-266-2648
Amit Sanghani
3500 Granada Ave, Santa Clara, CA 95051
408-249-5040

Publications

Us Patents

Power Droop Reduction Via Clock-Gating For At-Speed Scan Testing

US Patent:
8522190, Aug 27, 2013
Filed:
Apr 11, 2012
Appl. No.:
13/444780
Inventors:
Amit Sanghani - San Jose CA, US
Bo Yang - Santa Clara CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06F 11/22
G06F 17/50
US Classification:
716136, 716103, 716104, 716106, 716108, 716109
Abstract:
A clock gating mechanism controls power within an integrated circuit device. One or more clock gating circuits are configured to couple a system clock to a different portion of the integrated circuit device. A logic circuit applies an enabling signal to one of the clock gating circuits to control whether the system clock passes through the clock gating circuit to a portion of the integrated circuit device associated with the clock gating circuit. A plurality of scan flip-flops is configured to provide a binary code to the logic circuit, where the binary code indicates to the logic circuit that the enabling signal should be applied to the clock gating circuit. One advantage of the disclosed technique is that power droop during at-speed testing of a device is reduced without significantly increasing the quantity of test vectors or reducing test coverage, resulting in greater test yields and lower test times.

Method And Apparatus For Scan Test Of Sram For Microprocessors Without Full Scan Capability

US Patent:
5896396, Apr 20, 1999
Filed:
Jun 23, 1997
Appl. No.:
8/880929
Inventors:
Amit D. Sanghani - Santa Clara CA
Sridhar Narayanan - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G06F 1100
US Classification:
371 211
Abstract:
An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A third clocked flip-flop has a third flip-flop data input coupled to an inversion of the second flip-flop output, a third flip-flop scan-in input, a clock input coupled to the signal source, a scan enable input latched low, and a third flip-flop output, the third flip-flop inverting the third flip-flop data input at the third flip-flop output.

Automatic Test Pattern Generation Modeling For Lssd To Interface With Muxscan

US Patent:
6477684, Nov 5, 2002
Filed:
Jul 7, 2000
Appl. No.:
09/611734
Inventors:
Amit D. Sanghani - San Jose CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 1750
US Classification:
716 4, 716 5, 716 6
Abstract:
A model of a LSSD storage element and non-LSSD storage element interface for use with an automatic test pattern generator has been developed. The model includes a master element, a slave element, and a master observe module. The master observe module alternatively selects the input signal for the master element and the output signal from the slave element.

Apparatus For Scan Test Of Sram For Microprocessors Having Full Scan Capability

US Patent:
6047386, Apr 4, 2000
Filed:
Nov 5, 1998
Appl. No.:
9/187275
Inventors:
Amit D. Sanghani - Santa Clara CA
Narayanan Sridhar - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G06F 1300
G06F 1126
US Classification:
714 30
Abstract:
An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. An AND gate has a first input coupled to an inversion of the scan enable signal, a second input coupled to the output of the second flip-flop, and an output coupled to a write enable input to the SRAM.

Method And Apparatus For Scan Test Of Sram For Microprocessor Without Full Scan Capability

US Patent:
6014762, Jan 11, 2000
Filed:
Jun 23, 1997
Appl. No.:
8/880230
Inventors:
Amit D. Sanghani - Santa Clara CA
Narayanan Sridhar - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G11C 2900
G01R 3128
US Classification:
714718
Abstract:
An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A third clocked flip-flop has a third flip-flop data input coupled to an inversion of the second flip-flop output, a third flip-flop scan-in input, a clock input coupled to the signal source, a scan enable input latched low, and a third flip-flop output, the third flip-flop inverting the third flip-flop data input at the third flip-flop output.

Reinstate Apparatus And Method To Recreate Data Background For Testing Sram

US Patent:
6629275, Sep 30, 2003
Filed:
Feb 25, 2000
Appl. No.:
09/513662
Inventors:
Rahesh Y Pendurkar - Sunnyvale CA
Amit D. Sanghani - San Jose CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G01R 3128
US Classification:
714726, 714720
Abstract:
A system for recreating a data background to test memory designs for macros includes a macro, a first multiplexer, and a second multiplexer. The macro includes a plurality of flip-flops. The first multiplexer has a first input coupled to the macro output and a second input coupled to an inverted version of the macro output. The first multiplexer receives a control signal that selects between the macro output and the inverted version of such output to produce a first multiplexer output. A second multiplexer, coupled to the first multiplexer output and a normal scan input signal, receives a select signal that selects between the first multiplexer output and the normal scan input signal to generate a second multiplexer output, which is coupled to the macro input. A method for recreating a data background to test memory designs for a macro size defined by a plurality of flip-flops also is described.

Apparatus For Scan Test Of Sram For Microprocessors Having Full Scan Capability

US Patent:
5881218, Mar 9, 1999
Filed:
Jun 23, 1997
Appl. No.:
8/880930
Inventors:
Amit D. Sanghani - Santa Clara CA
Narayanan Sridhar - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G06F 1100
US Classification:
39518306
Abstract:
An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. An AND gate has a first input coupled to an inversion of the scan enable signal, a second input coupled to the output of the second flip-flop, and an output coupled to a write enable input to the SRAM.

Method For Scan Test Of Sram For Microprocessors Having Full Scan Capability

US Patent:
5923835, Jul 13, 1999
Filed:
Jun 23, 1997
Appl. No.:
8/880468
Inventors:
Amit D. Sanghani - Santa Clara CA
Narayanan Sridhar - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G06F 1100
G11C 2900
US Classification:
39518306
Abstract:
A method for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. An AND gate has a first input coupled to an inversion of the scan enable signal, a second input coupled to the output of the second flip-flop, and an output coupled to a write enable input to the SRAM.

FAQ: Learn more about Amit Sanghani

How is Amit Sanghani also known?

Amit Sanghani is also known as: Amit Dinesh Sanghani, Dinesh P Sanghani, Armit D Sanghani, Amit Samghani. These names can be aliases, nicknames, or other names they have used.

What is Amit Sanghani's current residential address?

Amit Sanghani's current known residential address is: 4901 Portmarnoch Ct, San Jose, CA 95138. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Amit Sanghani?

Previous addresses associated with Amit Sanghani include: 3945 Carracci Ln, San Jose, CA 95135; 11 Agapanthus St, Ladera Ranch, CA 92694; 255 Union Ave, Campbell, CA 95008; 392 Castlemaine Ct, San Jose, CA 95136; 3500 Granada Ave, Santa Clara, CA 95051. Remember that this information might not be complete or up-to-date.

Where does Amit Sanghani live?

San Jose, CA is the place where Amit Sanghani currently lives.

How old is Amit Sanghani?

Amit Sanghani is 52 years old.

What is Amit Sanghani date of birth?

Amit Sanghani was born on 1972.

What is Amit Sanghani's email?

Amit Sanghani has email address: asangh***@aol.com. Note that the accuracy of this email may vary and this is subject to privacy laws and restrictions.

What is Amit Sanghani's telephone number?

Amit Sanghani's known telephone numbers are: 408-223-2648, 949-218-3040, 408-559-1621, 408-266-2648, 408-249-5040, 408-605-2898. However, these numbers are subject to change and privacy restrictions.

How is Amit Sanghani also known?

Amit Sanghani is also known as: Amit Dinesh Sanghani, Dinesh P Sanghani, Armit D Sanghani, Amit Samghani. These names can be aliases, nicknames, or other names they have used.

Possible Relatives

Meera Sanghani Mehul Sanghani Niru Sanghani Samir Sanghani Siddharth Sanghani Sunil Sanghani Amit Khan Amit Klein Amit Stern Amit Kumar Amit Meir Amit Merchant Amit Levy Amit Sukhram

People Directory:

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Copyright © 2024 Veripages Systems Inc. All rights reserved.

VpTS 71240415