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Vishal Anand

In the United States, there are 53 individuals named Vishal Anand spread across 31 states, with the largest populations residing in New York, Texas, California. These Vishal Anand range in age from 40 to 54 years old. Some potential relatives include Yungee Kim, Josh Young, Jessica Johnson. You can reach Vishal Anand through various email addresses, including kashyapraj***@hotmail.com, vishal.an***@netscape.net, vishal.an***@comcast.net. The associated phone number is 609-208-9353, along with 6 other potential numbers in the area codes corresponding to 718, 650, 425. For a comprehensive view, you can access contact details, phone numbers, addresses, emails, social media profiles, arrest records, photos, videos, public records, business records, resumes, CVs, work history, and related names to ensure you have all the information you need.

Public information about Vishal Anand

Resumes

Resumes

Practice Director

Vishal Anand Photo 1
Location:
30 Old Towne Rd, Cheshire, CT 06410
Industry:
Computer Software
Work:
Iris Software
Practice Director Birlasoft
Na Practice Head, Data and Analytics Cognizant Technology Solutions
Consultant Ge Nov 2002 - Jun 2004
Data Warehouse Lead Icici Bank May 2002 - Nov 2002
Dw Architect Hughes Telecom Nov 2001 - Jun 2002
Dw Team Member Tata Consultancy Services Apr 2000 - Dec 2001
Module Lead In Tcs
Education:
T.a.pai Management Institute, Manipal 2010 - 2012
Manipal Academy of Higher Education 2003 - 2007
Bachelor of Engineering, Bachelors, Computer Science St. Michael's High School, Digha Ghat Patna 1989 - 2001
Assam University 1998
Bachelors, Bachelor of Arts National Institute of Technology 1998
Bachelors, Bachelor of Arts National Institute of Technology Silchar 1994 - 1998
Bachelors, Electronics Kendriya Vidyalaya 1989 - 1994
Skills:
Sap R/3, Etl, Data Warehousing, Master Data Management, Requirements Analysis, Cognos, Business Intelligence, Business Objects, Software Project Management, Oracle, Data Modeling, Agile Methodologies, Data Integration, Solution Architecture, Business Analysis, Dimensional Modeling, Informatica, Enterprise Architecture, Sdlc, Data Warehouse Architecture, Databases, Pl/Sql, Requirements Gathering, Db2, Data Migration, Pre Sales, Software Development Life Cycle, Sql, Project Management, It Strategy, Vendor Management, Integration, Management, Global Delivery, Java, Unix, Team Management, Consulting, Business Strategy

Sales Manager

Vishal Anand Photo 2
Location:
Cedar Park, TX
Industry:
Utilities
Work:
The Goodyear Tire & Rubber Company
Assistant Manager Birla Tyre Mar 2011 - Apr 2015
Business Manager Roca Btahroom Products Jan 2010 - Mar 2011
Management Trainee Bajaj Electricals Ltd May 2009 - Jul 2009
Summer Trainee May 2009 - Jul 2009
Sales Manager
Education:
Empi Business School 2008 - 2010
Master of Business Administration, Masters, Marketing
Skills:
Customer Service, Sales Operations, Financial Analysis, Financial Reporting, Management, Team Management, Mis, Market Research, Business Development, New Business Development, Sales, Channel Partners, Marketing Strategy, Negotiation, Competitive Analysis

Principal Software Engineer

Vishal Anand Photo 3
Location:
San Francisco, CA
Industry:
Computer Software
Work:
Mastercard
Principal Software Engineer Mastercard May 1, 2013 - May 2017
Leader, Software Engineer Bt Sep 2012 - Apr 2013
Senior Consultant Fico Mar 2011 - Sep 2012
Software Engineer Ii Xprotean, Inc. Jan 2010 - Apr 2011
Senior Software Engineer Exeter Group Jul 2007 - Jan 2010
It Consultant Bea Systems Jan 2007 - Jun 2007
Intern
Education:
National Institute of Technology Karnataka 2004 - 2007
St. Paul's School
Skills:
Web Services, Java Enterprise Edition, Spring, Java, Xml, Weblogic, Core Java, Hibernate, Design Patterns, Spring Framework, Agile Methodologies, Oracle, J2Ee Application Development, Struts, Python, Soa, Test Automation, Jsf

Liquidity Risk Analyst

Vishal Anand Photo 4
Location:
New York, NY
Industry:
Information Technology And Services
Work:
Oracle
Liquidity Risk Analyst Oracle Feb 1, 2014 - Jul 2013
Senior Principal Consultant at Oracle Financial Services Software Inc State Bank of India Apr 2002 - Oct 2010
Manager
Education:
Jamshedpur Cooperative College 1995 - 1998
Bachelors, Bachelor of Science, Mathematics
Skills:
Business Analysis, Requirements Analysis, Business Intelligence, Risk Management, Oracle, Requirements Gathering, Pl/Sql, Data Warehousing, Solution Architecture, Sql, Credit Risk, Banking, Basel Ii, Business Requirements, Management, Business Process, Software Development Life Cycle, Oracle E Business Suite, Oracle Applications
Languages:
English
Hindi
Certifications:
Financial Risk Manager
Cfa Level Ii Candidate
Certified Associate From the Indian Institute of Bankers (Caiib)
Diploma In Treasury, Investment and Risk Management
National Stock Exchange (Nse, Mumbai) Certified Market Professional
National Stock Exchange Certification In Financial Market (Ncfm) – Nsdl Depository Operations, Derivatives Market (Dealers), Capital Market (Dealers) and Securities Market Module.

Nlp Research, Data Scientist O365

Vishal Anand Photo 5
Location:
New York, NY
Industry:
Computer Software
Work:
Microsoft
Nlp Research, Data Scientist O365 Columbia University In the City of New York Sep 2017 - Mar 2019
Grad Student - Ca Fellow - Full Tuition Waiver, 3.92 Uber May 2018 - Aug 2018
Machine Learning Intern Visa Aug 2015 - Aug 2017
Senior Sw Engineer Google May 2015 - Aug 2015
Google Summer of Code Goldman Sachs May 19, 2014 - Jul 25, 2014
Securities Strats Summer Analyst The University of Manchester May 2013 - Jul 31, 2013
Summer Research Intern
Education:
Columbia University In the City of New York 2017 - 2018
Masters, Computer Science Stanford University 2016 - 2016
Indian Institute of Technology, Guwahati 2011 - 2015
Bachelors, Computer Science, Engineering, Computer Science and Engineering Delhi Public School, Bokaro Steel City 2009 - 2011
Saint Lawrence School Tentoloi 2008 - 2009
Delhi Public School Bokaro
Saint Lawrence School,Tentoloi
Saint Lawrence School
Skills:
C++, C, Algorithms, Data Structures, Matlab, Java, Python, Html, Microsoft Office, Programming, Machine Learning, Php, Simulations, Mysql, Linux, Analytics, Scala, Coding Theory, Violin, Javascript, Solving Rubik's Cube, Karate, Tensorflow, Cuda, Python, Trading Systems, Algorithm Analysis, System Architecture, Git
Languages:
English
Hindi
Oriya

Vishal Anand

Vishal Anand Photo 6
Position:
Senior Project Manager - EIM (DW/BI) Practice at Cognizant Technology Solutions
Location:
Cleveland/Akron, Ohio Area
Industry:
Computer Software
Work:
Cognizant Technology Solutions - Cleveland/Akron, Ohio Area since May 2012
Senior Project Manager - EIM (DW/BI) Practice Cognizant Technology Solutions Nov 2009 - May 2012
DW & BI Manager Cognizant Technology Solutions 2005 - Oct 2009
Sr Associate GE Nov 2002 - Jun 2004
Data Warehouse Lead ICICI Bank May 2002 - Nov 2002
DW Architect Hughes Telecom Nov 2001 - Jun 2002
DW Team Member TCS / GEAE Apr 2000 - Dec 2001
Module Lead in TCS
Education:
National Institute of Technology - Silchar 1994 - 1998
Bachelors in Engg, Electronics and Telcommunications Kendriya Vidyalaya 1989 - 1994
High School
Skills:
SAP R/3, ETL, Data Warehousing, Master Data Management, Requirements Analysis, Cognos, Business Intelligence, Business Objects, Software Project Management, Oracle, Data Modeling, Agile Methodologies, Data Integration, Solution Architecture, Business Analysis, Dimensional Modeling, Informatica

Consultant

Vishal Anand Photo 7
Location:
Issaquah, WA
Industry:
Information Technology And Services
Work:
Accenture Analytics
Consultant Tata Consultancy Services Apr 2017 - Jul 2018
It Analyst Tata Consultancy Services Feb 1, 2016 - Mar 2017
System Engineer Tolexo Sep 2015 - Jan 2016
Data Engineer Ii Infosys Oct 2014 - Aug 2015
Senior System Engineer Infosys Aug 2012 - Oct 2014
System Engineer
Education:
National Institute of Technology 2012
Masters National Institute of Technology Jamshedpur 2009 - 2012
Masters, Computer Applications, Computer Application Kalinga Institute of Information Technology 2006 - 2010
Bachelors, Bachelor of Technology Birla Institute of Technology, Mesra 2006 - 2009
Skills:
Pl/Sql, Core Java, Unix, Java Enterprise Edition, Jsp, Oracle Soa Suite, Weblogic, Servlets, Spring, Shell Scripting, Javascript, Iplanet Web Server, Datapower, Api Connect, Iib, Sterling Commerce, Web Service Development, Sql, Oracle, Mongodb, Hive, Hadoop, Teradata, Sqoop, R, Sdlc, Data Warehousing, Oozie, Yarn, Autosys, Sas Programming, Apache Spark
Interests:
Dancing
Cooking
Languages:
English
Hindi
Certifications:
Certified Safe 4 Agilist
Big Data Hadoop Foundations
Big Data Foundations
Big Data - Programming
Big Data Spark Foundations
Apache Spark Foundation
Data Analytics Foundation
Sas Fundamental
Sas Programming 1: Essentials
Exam 480: Programming In Html5 With Javascript and Css3
Introduction To R
Apache Spark & Scala Developer
Analyzing Big Data In R Using Apache Spark
Introduction To Sql For Data Sceince
Ibm
Tata Consultancy Services

North America Country Head

Vishal Anand Photo 8
Location:
15446 Del Red Rd, Redmond, WA
Industry:
Information Technology And Services
Work:
Globallogic
North America Country Head Brillio Feb 1, 2016 - Apr 2019
Vice President and Regional Head- West Cognizant Technology Solutions Jan 2014 - Jan 2016
Senior Director and Client Partner Retail and Consumer Goods Cognizant Technology Solutions Mar 2011 - Dec 2013
Client Partner North America Energy Practice Cognizant Technology Solutions Oct 2006 - Aug 2010
Director and Delivery Partner- Consumer Goods Midwest Region Cognizant Technology Solutions Jun 2000 - Sep 2006
Account Manager and Senior Business Analyst Tata Infotech May 1997 - Mar 1998
Software Engineer
Education:
Indian Institute of Management, Lucknow May 1998 - 2000
Master of Business Administration, Masters Indian Institute of Technology (Banaras Hindu University), Varanasi
Skills:
Business Development, Crm, It Strategy, Business Analysis, Global Delivery, Pre Sales, Program Management, Consulting, Leadership, Outsourcing, Requirements Analysis, Software Project Management, Management, Vendor Management, P&L Management, Business Intelligence, Strategy, Business Process, Business Strategy, Business Process Improvement, Team Management, Customer Relationship Management, Management Consulting, Service Delivery, Change Management, Integration, Customer Relations, Business Management, People Management, Project Management, Sdlc, Solution Architecture, Agile Application Development, Digital Experiences
Interests:
Traveling
Investing
Reading
Certifications:
Blockchain Basics
Agile Development Practices
Planning An Aws Solution

Phones & Addresses

Name
Addresses
Phones
Vishal Anand
309-796-3962
Vishal Anand
240-246-7925
Vishal Anand
425-985-1870
Vishal Anand
609-689-3002
Vishal Anand
732-422-4515
Vishal Anand
609-275-4610, 609-799-0842, 609-799-5878

Business Records

Name / Title
Company / Classification
Phones & Addresses
Vishal Anand
Business Development Director
INHERENT TECHNOLOGIES LLC
Custom Computer Programing
4341 W Dublin St, Chandler, AZ 85226
480-838-9696
Vishal Anand
Bhagwati Petroleum, LLC
Convenience Store/gas Station
Dothan, AL
Vishal Anand
Family And General Dentistry, Principal
Anand Vishal DDS PC Dr
Dentist's Office
10500 Wakeman Dr, Fredericksburg, VA 22407
Vishal Anand
Anand Petroleum, LLC
CONVENIENCE STORE/GAS STATION
Dothan, AL
Vishal Anand
Vishal, LLC
RESTAURANT FRANCHISE BUSINESS
Dothan, AL
Vishal Anand
VRG REAL ESTATE HOLDINGS, LLC
4442 E Palo Verde Dr, Phoenix, AZ 85018
Vishal Anand
Director, President
123 FRANCHISING INC
5012 Shoreway Loop #104, Orlando, FL 32819
PO Box 1136, Gotha, FL 34734
Vishal Anand
Secretary, Treasurer, Director, President
ILFY INC
4024 Breakview Dr #409, Orlando, FL 32819

Publications

Us Patents

Method Of And System For Allowing A Computer System To Access Cacheable Memory In A Non-Cacheable Manner

US Patent:
6134641, Oct 17, 2000
Filed:
Mar 20, 1998
Appl. No.:
9/045469
Inventors:
Vishal Anand - Fremont CA
Assignee:
VSLI Technology, Inc. - San Jose CA
International Classification:
G06F 1202
US Classification:
711202
Abstract:
A method of and a system for allowing cacheable system memory to be accessed in a non-cacheable manner. In one embodiment of the present invention, a computer system is tricked during POST (Power-On Self-Test) to reserve a first region in a non-cacheable address space for a virtual peripheral device. The computer system is then tricked during operating system startup to reserve a second region in a cacheable address space. In the present embodiment, the first region is then mapped to the second region such that accesses to the first region is automatically forwarded to the second region. As a result, objectives of the present invention are achieved as cacheable memory may be accessed via accessing non-cacheable memory of the computer system.

Method Of Representing A Generic Format Header Using Continuous Bytes And An Apparatus Thereof

US Patent:
2015037, Dec 24, 2015
Filed:
Jun 19, 2014
Appl. No.:
14/309619
Inventors:
- San Jose CA, US
Vishal Anand - Saratoga CA, US
International Classification:
H04L 29/08
H04L 29/06
Abstract:
Embodiments of the apparatus for modifying packet headers relate to a rewrite engine that represents each protocol header of packets in a generic format specific to that protocol to enable programmable modifications of packets, resulting in hardware and software flexibility in modifying packet headers. Software programs generic formats in a hardware table for various protocols. The rewrite engine is able to detect missing fields from a protocol header and is able to expand the protocol header to a maximum size such that the protocol header contains all possible fields of that protocol. Each of the fields has the same offset irrespective of which variation of the protocol the protocol header corresponds to. The expanded protocol header is represented by a data structure that is independent of a size of the protocol header.

Interface And Process For Handling Out-Of-Order Data Transactions And Synchronizing Events In A Split-Bus System

US Patent:
6363466, Mar 26, 2002
Filed:
Sep 13, 1999
Appl. No.:
09/394395
Inventors:
Vishal Anand - Fremont CA
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
G06F 1200
US Classification:
711169, 711151, 711158, 710112
Abstract:
An interface and process for re-ordering data transactions between a master device and a target device. The present invention applies to target devices that interface to master devices such that both masters and slaves are capable of handling the re-ordering of outstanding requests. In such an interface where data transactions can be in any order, certain events may occur that force the reordering to be limited to either before or after the event. These events, also referred to as synchronizing events herein, require that transactions sampled before the event must be completed before transactions sampled after the event are completed. The present invention is capable of handling such synchronizing events while maximizing reordering to gain maximum performance benefits.

Method Of Modifying Packets To A Generic Format For Enabling Programmable Modifications And An Apparatus Thereof

US Patent:
2015037, Dec 24, 2015
Filed:
Jun 19, 2014
Appl. No.:
14/309603
Inventors:
- San Jose CA, US
Vishal Anand - Saratoga CA, US
Tsahi Daniel - Palo Alto CA, US
Gerald Schmidt - San Jose CA, US
International Classification:
H04L 29/06
Abstract:
Embodiments of the apparatus for modifying packet headers relate to a rewrite engine that represents each protocol header of packets in a generic format specific to that protocol to enable programmable modifications of packets, resulting in hardware and software flexibility in modifying packet headers. Software programs generic formats in a hardware table for various protocols. The rewrite engine is able to detect missing fields from a protocol header and is able to expand the protocol header to a maximum size such that the protocol header contains all possible fields of that protocol. Each of the fields has the same offset irrespective of which variation of the protocol the protocol header corresponds to. In a bit vector, all newly added fields are marked invalid (represented by 0), and all existing fields are marked valid (represented by 1). Software modification commands allow data to be replaced, removed and inserted.

Two Modes Of A Configuration Interface Of A Network Asic

US Patent:
2016011, Apr 28, 2016
Filed:
Oct 22, 2014
Appl. No.:
14/521354
Inventors:
- San Jose CA, US
Harish Krishnamoorthy - San Jose CA, US
Gerald Schmidt - San Jose CA, US
Vishal Anand - Saratoga CA, US
International Classification:
G06F 13/40
G06F 13/42
Abstract:
Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.

Optimized Cpu-Memory High Bandwidth Multibus Structure Simultaneously Supporting Design Reusable Blocks

US Patent:
6377581, Apr 23, 2002
Filed:
May 14, 1998
Appl. No.:
09/079990
Inventors:
Vishal Anand - Fremont CA
Desi Rhoden - Phoenix AZ
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
H04L 1266
US Classification:
370402, 710129
Abstract:
An optimized CPU-memory high bandwidth multibus structure simultaneously supporting design reusable blocks. A system in accordance with the present invention communicatively couples the internal components (e. g. , CPU, memory, etc. ) and peripheral devices (e. g. , display, keyboard, etc. ) of a computer system by dividing the components into two logical subdivisions. One subdivision includes the memory and CPU(s) of the computer system while the other subdivision includes the remaining components. In accordance with the present invention, each subdivision of components is interconnected to the other components of its subdivision by a bus scheme. Both subdivision bus schemes are interconnected by circuitry referred to as a bridge, which enables them to intercommunicate. As such, the components connected to the separate subdivision bus schemes are able to intercommunicate. By implementing the intercommunication of computer system components in this manner, a substantial part of the interconnection circuitry of the computer system is typically reusable when significant modifications are subsequently implemented within future related computer systems.

Two Modes Of A Configuration Interface Of A Network Asic

US Patent:
2018024, Aug 30, 2018
Filed:
May 2, 2018
Appl. No.:
15/969681
Inventors:
- San Jose CA, US
Harish Krishnamoorthy - San Jose CA, US
Gerald Schmidt - San Jose CA, US
Vishal Anand - Saratoga CA, US
International Classification:
G06F 13/40
G06F 13/42
Abstract:
Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.

Technologies For Network Application Programming With Field-Programmable Gate Arrays

US Patent:
2019001, Jan 10, 2019
Filed:
Jul 7, 2017
Appl. No.:
15/644150
Inventors:
- Santa Clara CA, US
Thomas E. Willis - Redwood City CA, US
Pat Wang - San Jose CA, US
Vishal Anand - San Jose CA, US
Hung Nguyen - San Jose CA, US
Varsha Apte - San Jose CA, US
International Classification:
G06F 9/45
Abstract:
Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.

FAQ: Learn more about Vishal Anand

How is Vishal Anand also known?

Vishal Anand is also known as: Anand Visal, Anand Vishal. These names can be aliases, nicknames, or other names they have used.

Who is Vishal Anand related to?

Known relatives of Vishal Anand are: Nitya Nand, Sarojni Nand, Vishwa Nand, Anish Nand, Devika Anand, Nand Pranish. This information is based on available public records.

What are Vishal Anand's alternative names?

Known alternative names for Vishal Anand are: Nitya Nand, Sarojni Nand, Vishwa Nand, Anish Nand, Devika Anand, Nand Pranish. These can be aliases, maiden names, or nicknames.

What is Vishal Anand's current residential address?

Vishal Anand's current known residential address is: 32779 Sumac St, Union City, CA 94587. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Vishal Anand?

Previous addresses associated with Vishal Anand include: 625 South Ave, Staten Island, NY 10303; 581 Connemara Way, Sunnyvale, CA 94087; 32779 Sumac St, Union City, CA 94587; 20517 Ne 33Rd Ct, Sammamish, WA 98074; 4261 Hampton St, Elmhurst, NY 11373. Remember that this information might not be complete or up-to-date.

Where does Vishal Anand live?

Union City, CA is the place where Vishal Anand currently lives.

How old is Vishal Anand?

Vishal Anand is 42 years old.

What is Vishal Anand date of birth?

Vishal Anand was born on 1981.

What is Vishal Anand's email?

Vishal Anand has such email addresses: kashyapraj***@hotmail.com, vishal.an***@netscape.net, vishal.an***@comcast.net, vishal.an***@msn.com, vian***@hotmail.com. Note that the accuracy of these emails may vary and they are subject to privacy laws and restrictions.

What is Vishal Anand's telephone number?

Vishal Anand's known telephone numbers are: 609-208-9353, 718-370-3511, 650-967-2660, 425-985-1870, 646-515-4496, 425-392-7007. However, these numbers are subject to change and privacy restrictions.

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