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Steve Eaton

In the United States, there are 448 individuals named Steve Eaton spread across 49 states, with the largest populations residing in California, Texas, Florida. These Steve Eaton range in age from 45 to 76 years old. Some potential relatives include Angela Welch, Steve Eaton, Michael Helvey. You can reach Steve Eaton through various email addresses, including connie***@aol.c0m, tea***@onebox.com, loea***@aol.com. The associated phone number is 919-732-3625, along with 6 other potential numbers in the area codes corresponding to 254, 620, 352. For a comprehensive view, you can access contact details, phone numbers, addresses, emails, social media profiles, arrest records, photos, videos, public records, business records, resumes, CVs, work history, and related names to ensure you have all the information you need.

Public information about Steve Eaton

Resumes

Resumes

Warehouse Systems Specialist

Steve Eaton Photo 1
Location:
Fresno, CA
Industry:
Warehousing
Work:
Graylift
Warehouse Systems Specialist
Education:
California State University, Fresno 1976 - 1979
Bachelors, Business
Skills:
Team Building, Customer Service, Sales Management, Inventory Management, Account Management, Logistics, Warehousing, New Business Development, Operations Management, Warehouse Management, Contract Negotiation, Negotiation, Process Improvement, Purchasing, Supply Chain, Supply Chain Management, Management, Strategic Planning

Chief Executive Officer

Steve Eaton Photo 2
Location:
20920 Hobson Rd southwest, Centralia, WA 98531
Industry:
Wholesale
Work:
College of Medical Training Feb 2008 - Oct 2013
Director of Operations Safety Nw Feb 2008 - Oct 2013
Chief Executive Officer Hsbc Nov 2004 - Feb 2008
Assistant Vice President
Education:
Lower Columbia College 1995 - 1997
Timberline High School
Lower Columbia College
Skills:
Management, Industrial Safety, Marketing, Customer Relations, Customer Service, Workplace Safety, Construction Safety

Owner

Steve Eaton Photo 3
Location:
Logan, UT
Industry:
Public Relations And Communications
Work:
Jon M. Huntsman School of Business
Director of Communications Jon M. Huntsman School of Business - Utah State University since 2006
Director of Communications Utah State University 2006 - 2010
Director of Communications
Education:
Brigham Young University 1979 - 1983
Print Journalism, Journalism
Skills:
Research, Public Relations, Media Relations, Press Releases, Social Media, Editing, Community Outreach, Corporate Communications, Copywriting, Internal Communications, Strategic Communications, Publications, Ap Style, Marketing, Newspapers, Interviews, Copy Editing, Storytelling, Newsletters, Magazines, Public Speaking
Languages:
French

Managing Director

Steve Eaton Photo 4
Location:
Atlanta, GA
Industry:
Venture Capital & Private Equity
Work:
Medforum Jan 2016 - Aug 2020
Member Board of Directors Millenial Medical Information Services Jun 2014 - Jul 2017
Member Board of Directors Edg Partners Jun 2014 - Jul 2017
Managing Director
Education:
Western Kentucky University 1968 - 1972
Bachelors, Bachelor of Arts, History, Political Science
Skills:
Private Equity, Venture Capital, Start Ups, Mergers and Acquisitions, Due Diligence, Business Strategy, Strategic Planning, Valuation, Management Consulting, New Business Development, Investment Banking, Corporate Finance, Business Development, Financial Analysis, Finance, Healthcare, Financial Modeling, Capital Markets, Entrepreneurship, Corporate Development

Sales Department Sales Representative

Steve Eaton Photo 5
Location:
Acworth, GA
Industry:
Packaging And Containers
Work:
Southeastern Paper Group
Sales Department Sales Representative
Education:
Samford University 1981 - 1985
Bachelors, Bachelor of Business Administration, Economics, Management
Skills:
Key Account Management

Agent

Steve Eaton Photo 6
Location:
Floyd, VA
Industry:
Real Estate
Work:
Coldwell Banker Townside, Realtors
Realtor Coldwell Banker Townside, Realtors
Agent Grand Home Furnishings Dec 2012 - Jul 2014
Sales Associate Snacks 4U Sep 1998 - Aug 2012
Owner Canteen Service Co. Oct 1994 - Aug 1998
Food Service and Vending Manager
Education:
Radford University 1976 - 1981
Bachelors, Bachelor of Science, Marketing Cherry Creek High School 1976
E. C. Glass High School 1976
Skills:
Sales, Sales Management, Marketing, Merchandising, Customer Service, Microsoft Office, Retail, Interior Design, Selling, Account Management, Customer Satisfaction, Furniture, Inventory Management, Social Networking, Time Management, Microsoft Excel, Microsoft Word, Negotiation, Contract Negotiation, Event Planning, Purchasing, Retail Sales, Real Estate Buyer Agent, Real Estate Transactions, Real Estate
Languages:
English

Senior Firmware Engineer At Ibm

Steve Eaton Photo 7
Location:
Raleigh, NC
Industry:
Information Technology And Services
Work:
Ibm
Senior Firmware Engineer at Ibm Ibm
Senior Firmware Engineer
Education:
University of Florida 1985 - 1989
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Ibm Desktop Pcs, Ibm Powerpc, Technical Leadership, Management, Project Management, Firmware, Embedded Software, Ibm Servers, Embedded Systems, Software Development, X86 Assembly, Computer Architecture, Powerpc Assembly, Linux, C++, C, Windows, Powerpc Architecture

Store Manager

Steve Eaton Photo 8
Location:
Bowling Green, KY
Industry:
Retail
Work:
Rural King Farm & Home Store
Retail Management Serv-U-Success
Manager City of Fountain Run May 2010 - Sep 2013
Mayor Dollar General Mar 2010 - Jan 2012
Manager Walmart Sep 1981 - Mar 2010
Co-Manager Rite Aid Sep 1981 - Mar 2010
Store Manager
Education:
Barren County High School
Skills:
Merchandising, Inventory Control, Store Management, Order Processing, Scheduling, Payroll, Store Operations, New Store Openings, Management, Loss Prevention

Business Records

Name / Title
Company / Classification
Phones & Addresses
Steve Eaton
Director
E.C. EATON & SON LEASING, INC
410 Dogwood Est, Booneville, MS 38829
Steve Eaton
Vice-President
U Eaton Inc
Concrete Contractor · Nonresidential Construction · Concrete Repair
11996 Rdg Rd, Denver, CO 80403
PO Box 7428, Denver, CO 80403
11996 Rdg Rd, Golden, CO 80403
303-880-5259
Steve Eaton
Manager
Riverwest Federal Credit Union
3856 Southwest Blvd, Tulsa, OK 74107
Steve Eaton
CFO
GREATER ATLANTA CHRISTIAN FOUNDATION, INC
Elementary/Secondary School
1575 Indian Trl Lilburn Rd, Norcross, GA 30093
Steve Eaton
Principal
Steve Eaton Productions
Motion Picture/Video Production
1928 S Springbrook Ln, Boise, ID 83706
Mr. Steve Eaton
Tennessee Siding Company
Roofing Contractors
181 Windermere Ln, Cleveland, TN 37323
423-595-4437, 423-728-5442
Steve Eaton
Principal
Rei Recreational Equipment Inc
Ret Sporting Goods/Bicycles Whol Industrial Equipment
2962 El Camino Real, Tustin, CA 92782
Steve Eaton
Principal
Pay Half Store
Ret Misc Merchandise
140 S Dearborn St, Chicago, IL 60603

Publications

Us Patents

Two-Bit Per I/O Line Write Data Bus For Ddr1 And Ddr2 Operating Modes In A Dram

US Patent:
7349289, Mar 25, 2008
Filed:
Jul 8, 2005
Appl. No.:
11/177537
Inventors:
Jon Allan Faue - Colorado Springs CO, US
Steve Eaton - San Jose CA, US
Michael Murray - San Jose CA, US
Assignee:
ProMOS Technologies Inc. - Hsinchu
International Classification:
G11C 7/22
G11C 7/10
G11C 11/4093
G11C 11/4096
US Classification:
365233, 365194, 365198, 365219, 365193, 36518905
Abstract:
A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.

High Capacitive Load And Noise Tolerant System And Method For Controlling The Drive Strength Of Output Drivers In Integrated Circuit Devices

US Patent:
7782080, Aug 24, 2010
Filed:
Sep 9, 2008
Appl. No.:
12/207179
Inventors:
Steve Eaton - Colorado Springs CO, US
Assignee:
ProMOS Technologies Pte.Ltd. - Singapore
International Classification:
H03K 17/16
US Classification:
326 30, 326 87, 327108
Abstract:
An output driver calibration circuit includes a programmable drive strength output pullup driver including a strongest transistor and a number of other transistors, a programmable drive strength output pulldown driver including a strongest transistor and a number of other transistors, and a calibration circuit for generating a number of control signals for controlling the transistors in the output pullup driver and the transistors in the output pulldown driver, wherein the control signals are generated simultaneously, except for two the strongest driver transistors.

Data Sorting In Memories

US Patent:
7016235, Mar 21, 2006
Filed:
Mar 3, 2004
Appl. No.:
10/794782
Inventors:
Jon Allan Faue - Colorado Springs CO, US
Steve S. Eaton - San Jose CA, US
Assignee:
ProMOS Technologies Pte. Ltd.
International Classification:
G11C 7/00
US Classification:
36518902, 36523003, 365233, 3652385
Abstract:
A sorting circuit () transfers data between a first group of at least four lines () on which the data items are arranged based on their addresses, and a second group of lines (, WDR, WDF, WDR, WDF) on which the data items are arranged based on the order in which they are read or written in a burst operation. Six signals (SORT) and their complements are sufficient to control the sorting circuit for both the read and the write operations, and provide both the DDR and the DDR2 functionality.

Two-Bit Per I/O Line Write Data Bus For Ddr1 And Ddr2 Operating Modes In A Dram

US Patent:
2008013, Jun 12, 2008
Filed:
Jan 25, 2008
Appl. No.:
12/020352
Inventors:
Jon Allan Faue - Colorado Springs CO, US
Steve Eaton - Colorado Springs CO, US
Michael Murray - San Jose CA, US
Assignee:
ProMOS Technologies Inc. - Hsinchu
International Classification:
G11C 7/00
US Classification:
365219
Abstract:
A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.

Memory Refresh Methods And Circuits

US Patent:
2004003, Feb 26, 2004
Filed:
Aug 26, 2002
Appl. No.:
10/228530
Inventors:
Steve Eaton - San Jose CA, US
Michael Murray - San Jose CA, US
Li-Chun Li - Los Gatos CA, US
International Classification:
G11C007/00
US Classification:
365/222000
Abstract:
A memory performs a hidden refresh only at the end of a read operation or when the memory is disabled but is supposed to retain data in the disabled state. When the memory is in the enabled state, the refresh is not performed at the end of any operation other than read. This is done to ensure that execution of any memory access command will not be delayed by a refresh as long as the user follows certain timing rules. Other embodiments are also provided.

Multistage Parallel-To-Serial Conversion Of Read Data In Memories, With The First Serial Bit Skipping At Least One Stage

US Patent:
7054215, May 30, 2006
Filed:
Apr 2, 2004
Appl. No.:
10/816727
Inventors:
Steve S. Eaton - San Jose CA, US
Assignee:
ProMOS Technologies Pte. Ltd.
International Classification:
G11C 7/00
US Classification:
365220, 365194, 365233, 36518901, 36523008
Abstract:
Data bits are prefetched from memory cells in parallel and are read out serially. The memory includes multiple stages () of latches through which the parallel data is transferred before being read out serially. The multiple stages provide suitable delays to satisfy variable latency requirements (e. g. CAS latency in DDR). The first bit for the serial output bypasses the last stage (. M). In some embodiments, the control signals controlling the stages other than the last stage in their providing the first data bit to the memory output are not functions of the control signals controlling the last stage providing the subsequent data bits to the memory output.

Limited Output Address Register Technique Providing Selectively Variable Write Latency In Ddr2 (Double Data Rate Two) Integrated Circuit Memory Devices

US Patent:
7061823, Jun 13, 2006
Filed:
Aug 24, 2004
Appl. No.:
10/924546
Inventors:
Jon Allan Faue - Colorado Springs CO, US
Steve S. Eaton - San Jose CA, US
Assignee:
ProMOS Technologies Inc. - Hsinchu
International Classification:
G11C 8/00
US Classification:
36523008, 365233
Abstract:
A limited output address register technique for selectively variable write latency in double data rate 2 (DDR2) integrated circuit memory devices providing a reduced number of paths directly connected to the output. A chain of DQ flip-flops is disclosed which is only loaded on valid write address commands but shifts continually thereafter every clock cycle. Since new READ or WRITE commands cannot be issued on successive cycles, at any given point in the chain an address (or state) is valid for at least two cycles. Therefore, a selected point in the register chain can be used to satisfy the requirements for two different latencies. For DDR2, having N write latency cases, only ceil(N/2) access points to the write address output have to be provided thereby saving on-chip area and increasing speed. In a specific embodiment disclosed, DDR1 may also be supported.

Voltage-Controlled Analog Delay Locked Loop

US Patent:
7071745, Jul 4, 2006
Filed:
Feb 11, 2004
Appl. No.:
10/776366
Inventors:
John D. Heightley - Colorado Springs CO, US
Steve S. Eaton - San Jose CA, US
Assignee:
ProMOS Technologies, Inc. - Hsinchu
International Classification:
H03L 7/06
US Classification:
327158, 327149, 327161
Abstract:
An analog delay locked loop for receiving a reference clock signal and for generating a delayed output clock signal includes a voltage controlled delay line, a fixed delay line, a delay voltage control, a fast/slow latch, a phase detector, as well as reset and clock off circuits. The fast/slow latch generates three signals that are received by the delay voltage control: a “latched slow signal”, a “latched fast signal”, as well as a “latched fast to slow signal”. The phase detector generates “go fast” and “go slow” signals that are received by the fast/slow latch. The analog delay locked loop sets the initial delay of the delay line at or near its minimum value on start-up. The delay is then forced to increase from the minimum value until a locking condition is achieved independent of the phase relationship between the reference and delayed clock signals.

FAQ: Learn more about Steve Eaton

What are the previous addresses of Steve Eaton?

Previous addresses associated with Steve Eaton include: 189 Honey Ln, Waco, TX 76706; 204 Elizabeth St, Scott City, KS 67871; 25393 Lake Lindsey Rd, Brooksville, FL 34601; 3010 Berry St, Sioux City, IA 51103; 4006 Dixon Cir, Greenville, TX 75401. Remember that this information might not be complete or up-to-date.

Where does Steve Eaton live?

Farmington, MO is the place where Steve Eaton currently lives.

How old is Steve Eaton?

Steve Eaton is 67 years old.

What is Steve Eaton date of birth?

Steve Eaton was born on 1957.

What is Steve Eaton's email?

Steve Eaton has such email addresses: connie***@aol.c0m, tea***@onebox.com, loea***@aol.com, steve.ea***@collegeclub.com, sa***@hillarysbridal.com, recon***@hotmail.com. Note that the accuracy of these emails may vary and they are subject to privacy laws and restrictions.

What is Steve Eaton's telephone number?

Steve Eaton's known telephone numbers are: 919-732-3625, 254-662-5253, 620-872-0122, 352-796-1706, 712-252-3498, 903-454-2318. However, these numbers are subject to change and privacy restrictions.

How is Steve Eaton also known?

Steve Eaton is also known as: Steven J Eaton, Steven L Eaton. These names can be aliases, nicknames, or other names they have used.

Who is Steve Eaton related to?

Known relatives of Steve Eaton are: Angela Welch, Murril Eaton, Steve Eaton, Susan Eaton, Vera Eaton, Michael Helvey, Sarah Helvey. This information is based on available public records.

What are Steve Eaton's alternative names?

Known alternative names for Steve Eaton are: Angela Welch, Murril Eaton, Steve Eaton, Susan Eaton, Vera Eaton, Michael Helvey, Sarah Helvey. These can be aliases, maiden names, or nicknames.

What is Steve Eaton's current residential address?

Steve Eaton's current known residential address is: 16167 Brendon Dr, Farmington, MO 63640. Please note this is subject to privacy laws and may not be current.

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