Somnath Ghosh

In the United States, there are 22 individuals named Somnath Ghosh spread across 17 states, with the largest populations residing in California, New Jersey, Texas.

Public information about Somnath Ghosh

Resumes

Senior Advanced Software Architect

Location:

Atlanta, GA

Industry:

Computer Software

Work:

Microsoft Aug 2011 - Dec 2014
Consultant Accenture India Jul 2008 - Jul 2011
Senior Programmer Accenture Jul 2008 - Jul 2009
Programmer Honeywell Jul 2008 - Jul 2009
Senior Advanced Software Architect

Education:

Maulana Azad National Institute of Technology 2004 - 2008
Bachelors, Bachelor of Technology, Communication, Electronics

Skills:

Microsoft Sql Server

Pulmonary And Critical Care Consultant

Location:

Medford, OR

Industry:

Medical Practice

Work:

Rvmc
Pulmonary and Critical Care Consultant The University of Texas Health Science Center at Houston Jul 2008 - Jun 2011
Pulmonary and Critical Care Fellow Good Samaritan Hospital Baltimore 2005 - 2008
Medical Resident

Education:

University of Cincinnati 2002 - 2004
Master of Science, Masters, Medicine Loyola High School and Junior College 1984 - 1996

Skills:

Medicine, Critical Care, Healthcare, Medical Education, Internal Medicine, Pulmonology, Clinical Research, Treatment, Hospitals

Director Operations At Corporate It Solutions, Inc.

Position:

Director Operations at Corporate IT Solutions, Inc

Location:

Greater Denver Area

Industry:

Computer Software

Work:

Corporate IT Solutions, Inc since 2007
Director Operations

Education:

PMP, Agile Certified Practitioner (PMI-ACP), ScrumMaster (CSM), Scrum Practitioner (CSP) 2007 - 2012
MBA (Information Systems) University of Houston 1995 - 1997
MBA (MIS), Master in Business Administration (MBA) in Information Systems BS (Electronics Engineering) 1986 - 1990
BS (Electronics Engineering), Bachelor of Science (BS) in Electronics Engineering, India Microsoft Certified Technology Specialist (MCTS)

Intensivist At Asante Health System

Location:

1505 northwest Washington Blvd, Grants Pass, OR 97526

Industry:

Hospital & Health Care

Work:

Asante
Intensivist at Asante Health System

Somnath Ghosh

Location:

Denver, CO

Industry:

Information Technology And Services

Somnath Ghosh

Location:

3055 Rubino Cir, San Jose, CA 95125

Industry:

Computer Software

Work:

Princeton University
Senior Software Engineer

Education:

Princeton University 1994 - 1999
PhD, Computer EngineeringPhD on Code Analysis to Improve Cache Performance. Introduced Cache Miss Equations to Characterize, Study, and Improve Hardware Cache Behavior. Indian Institute of Technology, Kharagpur 1989 - 1993
B.Tech., Computer Sciece & EngineeringFinal Year Project: Designing and Implementing a RISC Processor Pipeline.

Skills:

Compilers, Gpgpu, Debugging, High Performance Computing, Algorithms, Computer Architecture, X86, Architecture, Embedded Systems, C++, Software Engineering, Software Development, C, Distributed Systems, Gpu, Opengl, Perl, Cuda, Opencl, Runtime Systems

Languages:

English

Coordinator

Work:

Coordinator

Somnath Ghosh

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Data provided by Veripages

Phones & Addresses

Name

Addresses

Phones

Somnath Ghosh

2600 Bay Area Blvd, Houston, TX 77058

Somnath Ghosh

4065 Braeswood Blvd, Houston, TX 77025

713-660-8490

Somnath Ghosh

1274 Madison Ln, Hockessin, DE 19707

Somnath Ghosh

4065 Braeswood Sq, Houston, TX 77025

713-660-8490

Somnath S Ghosh

4982 Ulster St, Denver, CO 80237

Somnath Ghosh

3055 Rubino Cir, San Jose, CA 95125

408-401-6231

Somnath S Ghosh

5116 Delaware St, Englewood, CO 80110

303-730-3753

Somnath Ghosh

San Jose, CA

408-873-8983, 408-289-8660

Publications

Us Patents

Top Via Interconnects With Wrap Around Liner

US Patent:

2021004, Feb 11, 2021

Filed:

Aug 9, 2019

Appl. No.:

16/536785

Inventors:

- Armonk NY, US
Nicholas Anthony Lanzillo - Troy NY, US
Christopher J. Penny - Saratoga Springs NY, US
Somnath Ghosh - Clifton Park NY, US
Robert Robison - Rexford NY, US
Lawrence A. Clevenger - Saratoga Springs NY, US

International Classification:

H01L 21/768
H01L 23/532
H01L 21/311
H01L 23/522
H01L 21/3213
H01L 21/288
H01L 23/528

Abstract:

A method includes patterning an interconnect trench in a dielectric layer. The interconnect trench has sidewalk and a bottom surface. A liner layer is deposited on the sidewalls and the bottom surface of the interconnect trench. The interconnect trench is filled with a first conductive metal material. The conducting metal material is recessed to below a top surface of the dielectric layer. A cap layer is deposited on a top surface of the first conductive metal material. The cap layer and the liner layer are of the same material. The method further includes forming a via on a portion of the interconnect trench.

Top Via With Hybrid Metallization

US Patent:

2021013, May 6, 2021

Filed:

Nov 4, 2019

Appl. No.:

16/672904

Inventors:

- Armonk NY, US
Nicholas Anthony Lanzillo - Troy NY, US
Christopher J. Penny - Saratoga Springs NY, US
SOMNATH GHOSH - CLIFTON PARK NY, US
Robert ROBISON - Rexford NY, US
Lawrence A. Clevenger - Saratoga Springs NY, US

International Classification:

H01L 21/768
H01L 23/532
H01L 23/522

Abstract:

Embodiments of the present invention are directed to fabrication methods and resulting structures for subtractively forming a top via using a hybrid metallization scheme. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a topmost surface of a first liner layer. The first liner layer can be positioned between the conductive line and a dielectric layer. A top via layer is formed on the recessed surface of the conductive line and a hard mask is formed over a first portion of the top via layer. A second portion of the top via layer is removed. The remaining first portion of the top via layer defines the top via. The conductive line can include copper while the top via layers can include ruthenium or cobalt.

Alias-Free Test For Dynamic Array Structures

US Patent:

6880154, Apr 12, 2005

Filed:

Jun 29, 2001

Appl. No.:

09/896936

Inventors:

Somnath Ghosh - San Jose CA, US
Rakesh Krishnaiyer - Santa Clara CA, US
Wei Li - Redwood Shores CA, US
Abhay Kanhere - Sunnyvale CA, US
Dattatraya Kulkarni - Santa Clara CA, US
John L. Ng - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F009/45

US Classification:

717151, 717145, 717154, 717155, 717140, 711105, 711169, 711170, 711173

Abstract:

An apparatus, method, and program product for optimizing code that contains dynamically-allocated memory. The aliasing behavior of internal pointers of dynamically-allocated memory is used to disambiguate memory accesses and to eliminate false data dependencies. It is determined whether a dynamically-allocated array will behave like a statically-allocated array throughout the entire program execution once it has been allocated. This determination is used to improve the instruction scheduling efficiency, which yields better performance.

Fully Aligned Top Vias

US Patent:

2021014, May 13, 2021

Filed:

Nov 8, 2019

Appl. No.:

16/678053

Inventors:

- Armonk NY, US
Koichi Motoyama - Clifton Park NY, US
Somnath Ghosh - Clifton Park NY, US
Christopher J. Penny - Saratoga Springs NY, US
Robert Robison - Rexford NY, US
Lawrence A. Clevenger - Saratoga Springs NY, US

International Classification:

H01L 21/768
H01L 23/522
H01L 23/532

Abstract:

A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.

Patterning Line Cuts Before Line Patterning Using Sacrificial Fill Material

US Patent:

2021021, Jul 8, 2021

Filed:

Jan 7, 2020

Appl. No.:

16/736478

Inventors:

- Armonk NY, US
Timothy Mathew Philip - Albany NY, US
Somnath Ghosh - Clifton Park NY, US
Robert Robison - Rexford NY, US

International Classification:

H01L 21/768
H01L 21/311
H01L 21/033

Abstract:

A method includes forming a dielectric layer on a semiconductor substrate, forming a hard mask layer on the dielectric layer, forming a sacrificial mandrel layer on the hard mask layer, depositing a sacrificial fill material in an opening in the sacrificial mandrel layer and utilizing the sacrificial fill material to selectively pattern the hard mask layer. The pattern defining first and second spaced openings in the hard mask layer. The method further includes etching the dielectric layer through the first and second openings in the hard mask layer to create first and second trenches in the dielectric layer separated by a dielectric segment of the dielectric layer.

Dynamic Prefetch Distance Calculation

US Patent:

7702856, Apr 20, 2010

Filed:

Nov 9, 2005

Appl. No.:

11/271415

Inventors:

Rakesh Krishnaiyer - Milpitas CA, US
Somnath Ghosh - Sunnyvale CA, US
Abhay Kanhere - Sunnyvale CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00
G06F 13/28

US Classification:

711137, 712207, 717151, 717158, 717160, 717161

Abstract:

The prefetch distance to be used by a prefetch instruction may not always be correctly calculated using compile-time information. In one embodiment, the present invention generates prefetch distance calculation code to dynamically calculate a prefetch distance used by a prefetch instruction at run-time.

Line Cut Patterning Using Sacrificial Material

US Patent:

2021026, Aug 26, 2021

Filed:

Feb 20, 2020

Appl. No.:

16/796079

Inventors:

- Armonk NY, US
Daniel James Dechene - Watervliet NY, US
Somnath Ghosh - Clifton Park NY, US
Robert Robison - Rexford NY, US

International Classification:

H01L 21/768
H01L 21/311
H01L 21/3213
H01L 21/033

Abstract:

A method for fabricating a semiconductor device includes forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate. The first line pattern has a pitch defined by a target line width and a minimum width of space between lines. The method further includes forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a first gap having the target line width, and forming a first plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer.

Via-Via Spacing Reduction Without Additional Cut Mask

US Patent:

2021026, Aug 26, 2021

Filed:

Feb 20, 2020

Appl. No.:

16/795718

Inventors:

- Armonk NY, US
Somnath Ghosh - Clifton Park NY, US
Hsueh-Chung Chen - Cohoes NY, US
Carl Radens - LaGrangeville NY, US
Lawrence A. Clevenger - Saratoga Springs NY, US

International Classification:

H01L 21/033

Abstract:

A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.

Videos & Images

Youtube

2009 Rec Semi-Final - Som V Shiv, 5Th Game

Duration:

3m 23s

Category:

Sports

Description:

Ghosh Somnath vs. Shiv Jayaraman. Recreational pool.

Sovanagar Nightangal United Club Sraswati Puja.

Duration:

29s

Category:

People & Blogs

Description:

Amader sovanagar er nightangal united club er eai pujo et jara join ache tara holo. Boni, anabik, somnath, chotku, arun, ghosh, don, debu, bikrom, ratul, and ebar theke join korlam ami(ponku) and chandan.

Part 2 - Anurekha Ghosh Performs Monsoon Voices (Classical Kathak Dance With Khayal)

Duration:

7m 11s

Category:

Entertainment

Description:

MONSOON VOICES (Part 2) A collaboration with Khayal singing with Classical Kathak dance portraying the various moods of the Monsoon season. Performed by Sandeep Nag who sang the Khayal bandishes in Raag Jayant Malhar, Anurekha Ghosh explores the various facets of classical Kathak dance in Vilambit l...

Aalor Pipasa

Duration:

2h 4m 55s

Category:

Movies

Description:

Aalor Pipasa was released on 1965 Bengali film starring Basanta Chowdhury, Sandhya Roy, Anup Kumar, Asha Debi, Anubha Gupta, Satindra Bhattacharya, Somnath Mondal, Sabita Singh, Bhanu Ghosh, Master Subrata, Samar Kumar. The Bengali film is directed by Tarun Majumdar. Hemanta Mukhopadhyay scored the ...

Hindusztni S Karnatikus Zene (1)

Duration:

4m 56s

Category:

Music

Description:

A felvtel 2011. mrcius 19 -n, szombaton kszlt Budapesten, a Trafo Kortrs Mvszetek Hzban. Az indiai klasszikus zennek szentelt est kt rszbl ll. Az els rsz a Tala, azaz a ritmus nyelve: Pandit Abhijit Banerjee -- Tabla, Pakhawaj, Somnath Roy -- Ghatam jtszott. A msodik, sznet utni...

Chuni Panna..title

Duration:

1m 5s

Category:

Entertainment

Description:

Screenplay Writen By Somnath Mukherjee & Directed by Jishu Dasgupta.

Hindusztni S Karnatikus Zene (2)

Duration:

8m 29s

Category:

Music

Description:

Hindusztni S Karnatikus Zene (3)

Duration:

8m 56s

Category:

Music

Description:

FAQ: Learn more about Somnath Ghosh

What is Somnath Ghosh's current residential address?

Somnath Ghosh's current known residential address is: 9187 S Madras Ct, Littleton, CO 80130. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Somnath Ghosh?

Previous addresses associated with Somnath Ghosh include: 2232 Kaitlins Ct, Ellicott City, MD 21043; 5609 Saddle Ridge Dr, Medford, OR 97504; 6550 Wetherole St Apt 1E, Rego Park, NY 11374; 1274 Madison Ln, Hockessin, DE 19707; 280 Marin Blvd Apt 19O, Jersey City, NJ 07302. Remember that this information might not be complete or up-to-date.

Where does Somnath Ghosh live?

Highlands Ranch, CO is the place where Somnath Ghosh currently lives.

How old is Somnath Ghosh?

Somnath Ghosh is 55 years old.

What is Somnath Ghosh date of birth?

Somnath Ghosh was born on 1968.

What is Somnath Ghosh's email?

Somnath Ghosh has such email addresses: lsmith***@yahoo.com, firoza_gh***@yahoo.com, shohini.gh***@worldnet.att.net. Note that the accuracy of these emails may vary and they are subject to privacy laws and restrictions.

What is Somnath Ghosh's telephone number?

Somnath Ghosh's known telephone numbers are: 614-214-1487, 201-658-7996, 408-401-6231, 720-217-8516, 614-848-9860, 614-889-1497. However, these numbers are subject to change and privacy restrictions.

How is Somnath Ghosh also known?

Somnath Ghosh is also known as: Somnath Ghosh, Somnath Ghoshshohini Ghosh, Somnath S Ghosh, Samnath Ghosh, Sumnat Ghosh, H Ghosh, Shohini S Ghosh, Ghosh Somnath, I A, Sudip Kettmann. These names can be aliases, nicknames, or other names they have used.

Who is Somnath Ghosh related to?

Known relatives of Somnath Ghosh are: Dipanjan Ghosh, Ganga Ghosh, Papri Ghosh, Pradip Ghosh, Rajib Ghosh, Rani Ghosh, Suparna Ghosh, Shohini Ghosh, Ranapati Ghosh, Didanjan Ghosh. This information is based on available public records.

What are Somnath Ghosh's alternative names?

Known alternative names for Somnath Ghosh are: Dipanjan Ghosh, Ganga Ghosh, Papri Ghosh, Pradip Ghosh, Rajib Ghosh, Rani Ghosh, Suparna Ghosh, Shohini Ghosh, Ranapati Ghosh, Didanjan Ghosh. These can be aliases, maiden names, or nicknames.

Ages	42 to 70
Phones	614-214-1487	201-658-7996	408-401-6231
Addresses	10622 Midway Dr, Frisco, TX 75035	2232 Kaitlins Ct, Ellicott City, MD 21043	5609 Saddle Ridge Dr, Medford, OR 97504
Business records	Director Operations / Corporate IT Solutions, Inc	Asst Project Manager / Cognizant Technology Solutions	Vice President / Jpmorgan Chase & Co.

Somnath Ghosh

What do we know about Somnath Ghosh

Public information about Somnath Ghosh

Resumes

Resumes

Senior Advanced Software Architect

Pulmonary And Critical Care Consultant

Director Operations At Corporate It Solutions, Inc.

Intensivist At Asante Health System

Somnath Ghosh

Somnath Ghosh

Coordinator

Somnath Ghosh

Phones & Addresses

Publications

Us Patents

Top Via Interconnects With Wrap Around Liner

Top Via With Hybrid Metallization

Alias-Free Test For Dynamic Array Structures

Fully Aligned Top Vias

Patterning Line Cuts Before Line Patterning Using Sacrificial Fill Material

Dynamic Prefetch Distance Calculation

Line Cut Patterning Using Sacrificial Material

Via-Via Spacing Reduction Without Additional Cut Mask

FAQ: Learn more about Somnath Ghosh

Possible Relatives