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Robert Bigwood

In the United States, there are 31 individuals named Robert Bigwood spread across 25 states, with the largest populations residing in Massachusetts, Florida, New Jersey. These Robert Bigwood range in age from 34 to 76 years old. Some potential relatives include Amber Bigwood, Christine Bigwood, Valerie Girouard. You can reach Robert Bigwood through various email addresses, including rbigw***@yahoo.com, lrobin***@caperegional.com, rbigw***@aol.com. The associated phone number is 503-591-3217, along with 6 other potential numbers in the area codes corresponding to 563, 910, 978. For a comprehensive view, you can access contact details, phone numbers, addresses, emails, social media profiles, arrest records, photos, videos, public records, business records, resumes, CVs, work history, and related names to ensure you have all the information you need.

Public information about Robert Bigwood

Phones & Addresses

Name
Addresses
Phones
Robert T Bigwood
413-499-4640
Robert W Bigwood
218-736-5493
Robert Bigwood
503-591-3217
Robert W Bigwood
218-739-2079
Robert Bigwood
563-243-4759
Robert Bigwood
609-770-7831
Robert C Bigwood
563-243-4759

Publications

Us Patents

Metal Via Processing Schemes With Via Critical Dimension (Cd) Control For Back End Of Line (Beol) Interconnects And The Resulting Structures

US Patent:
2019025, Aug 22, 2019
Filed:
May 3, 2019
Appl. No.:
16/402664
Inventors:
- Santa Clara CA, US
Mohit K. HARAN - Hillsboro OR, US
Charles H. WALLACE - Portland OR, US
Robert M. BIGWOOD - Hillsboro OR, US
Deepak S. RAO - Portland OR, US
Alexander F. KAPLAN - Portland OR, US
International Classification:
H01L 21/768
H01L 21/033
H01L 21/311
Abstract:
Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.

Pattern Decomposition Lithography Techniques

US Patent:
2020009, Mar 19, 2020
Filed:
Nov 22, 2019
Appl. No.:
16/692589
Inventors:
- Santa Clara CA, US
HOSSAM A. ABDALLAH - Portland OR, US
ELLIOT N. TAN - Portland OR, US
SWAMINATHAN SIVAKUMAR - Portland OR, US
OLEG GOLONZKA - Beaverton OR, US
ROBERT M. BIGWOOD - Hillsboro OR, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
H01L 23/00
G03F 1/36
H01L 21/027
G03F 1/70
G03F 7/00
G03F 7/40
G03F 7/20
H01L 21/02
H01L 21/263
H01L 27/02
G03F 1/50
G03F 7/16
H01L 21/306
H01L 21/308
Abstract:
Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

Pattern Decomposition Lithography Techniques

US Patent:
2014011, May 1, 2014
Filed:
Dec 29, 2011
Appl. No.:
13/976082
Inventors:
Charles H. Wallace - Portland OR, US
Hossam M. Abdallah - Portland OR, US
Elliot N. Tan - Portland OR, US
Swaminathan Sivakumar - Portland OR, US
Oleg Golonzka - Beaverton OR, US
Robert M. Bigwood - Hillsboro OR, US
International Classification:
H01L 21/263
H01L 27/02
H01L 21/02
G03F 7/20
US Classification:
257499, 355 67, 438694
Abstract:
Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may he arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

Pattern Decomposition Lithography Techniques

US Patent:
2021037, Dec 2, 2021
Filed:
Aug 17, 2021
Appl. No.:
17/404870
Inventors:
- Santa Clara CA, US
Hossam A. ABDALLAH - Portland OR, US
Elliot N. TAN - Portland OR, US
Swaminathan SIVAKUMAR - Portland OR, US
Oleg GOLONZKA - Beaverton OR, US
Robert M. BIGWOOD - Hillsboro OR, US
International Classification:
H01L 23/00
G03F 7/00
G03F 7/40
H01L 21/027
G03F 1/36
G03F 1/70
G03F 7/20
H01L 21/02
H01L 21/263
H01L 27/02
G03F 1/50
G03F 7/16
H01L 21/306
H01L 21/308
Abstract:
Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

Dummy Gate Patterning Lines And Integrated Circuit Structures Resulting Therefrom

US Patent:
2022041, Dec 29, 2022
Filed:
Jun 23, 2021
Appl. No.:
17/356056
Inventors:
- Santa Clara CA, US
Biswajeet GUHA - Hillsboro OR, US
Mohit K. HARAN - Hillsboro OR, US
Vadym KAPINUS - Portland OR, US
Robert BIGWOOD - Hillsboro OR, US
Nidhi KHANDELWAL - Portland OR, US
Henning HAFFNER - Beaverton OR, US
Kevin FISCHER - Hillsboro OR, US
International Classification:
H01L 23/528
H01L 27/088
H01L 21/033
H01L 21/8234
Abstract:
Dummy gate patterning lines, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a first gate line along a first direction. A second gate line is parallel with the first gate line along the first direction. A third gate line extends between and is continuous with the first gate line and the second gate line along a second direction, the second direction orthogonal to the first direction.

Data Compression For Ebeam Throughput

US Patent:
2017006, Mar 9, 2017
Filed:
Dec 19, 2014
Appl. No.:
15/122398
Inventors:
- Santa Clara CA, US
Yan A. BORODOVSKY - Portland OR, US
Mark C. PHILLIPS - Portland OR, US
Robert M. BIGWOOD - Hillsboro OR, US
International Classification:
H01L 21/311
H01J 37/317
H01J 37/04
H01L 21/027
H01J 37/302
Abstract:
Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a method of data compression or data reduction for e-beam tool simplification involves providing an amount of data to write a column field and to adjust the column field for field edge placement error on a wafer, wherein the amount of data is limited to data for patterning approximately 10% or less of the column field. The method also involves performing e-beam writing on the wafer using the amount of data.

Process Window-Based Correction For Photolithography Masks

US Patent:
2006009, May 4, 2006
Filed:
Oct 29, 2004
Appl. No.:
10/977421
Inventors:
Robert Bigwood - Hillsboro OR, US
Shem Ogadhoh - Beaverton OR, US
Joseph Brandenburg - Portland OR, US
International Classification:
G06F 17/50
US Classification:
716019000, 716004000, 716021000
Abstract:
A correction for photolithography masks used in semiconductor and micro electromechanical systems is described. The correction is based on process windows. In one example, the invention includes evaluating a segment of an idealized photolithography mask at a plurality of different possible process variable values to estimate a corresponding plurality of different photoresist edge positions, comparing the estimated edge positions to a minimum critical dimension, and moving the segment on the idealized photolithography mask if the estimated edge positions do not satisfy the minimum critical dimension.

Pattern Decomposition Lithography Techniques

US Patent:
2017013, May 18, 2017
Filed:
Jan 30, 2017
Appl. No.:
15/419147
Inventors:
- Santa Clara CA, US
HOSSAM M. ABDALLAH - Portland OR, US
ELLIOT N. TAN - Portland OR, US
SWAMINATHAN SIVAKUMAR - Portland OR, US
OLEG GOLONZKA - Beaverton OR, US
ROBERT M. BIGWOOD - Hillsboro OR, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
G03F 1/36
G03F 7/20
G03F 1/50
H01L 21/027
H01L 21/308
Abstract:
Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

FAQ: Learn more about Robert Bigwood

How old is Robert Bigwood?

Robert Bigwood is 45 years old.

What is Robert Bigwood date of birth?

Robert Bigwood was born on 1978.

What is Robert Bigwood's email?

Robert Bigwood has such email addresses: rbigw***@yahoo.com, lrobin***@caperegional.com, rbigw***@aol.com, robertbigw***@webtv.net, robertbigw***@hotmail.com, dinky_***@yahoo.com. Note that the accuracy of these emails may vary and they are subject to privacy laws and restrictions.

What is Robert Bigwood's telephone number?

Robert Bigwood's known telephone numbers are: 503-591-3217, 563-243-4759, 910-794-4097, 978-827-5014, 352-307-4875, 305-367-4870. However, these numbers are subject to change and privacy restrictions.

How is Robert Bigwood also known?

Robert Bigwood is also known as: Bobby Bigwood, Rob W Bigwood, Bob W Bigwood. These names can be aliases, nicknames, or other names they have used.

Who is Robert Bigwood related to?

Known relatives of Robert Bigwood are: Elisa Conway, Thomas Conway, John Fisher, Judith Fisher, Rachel Fisher, Glenn Cafaro, Charles Cafaro. This information is based on available public records.

What are Robert Bigwood's alternative names?

Known alternative names for Robert Bigwood are: Elisa Conway, Thomas Conway, John Fisher, Judith Fisher, Rachel Fisher, Glenn Cafaro, Charles Cafaro. These can be aliases, maiden names, or nicknames.

What is Robert Bigwood's current residential address?

Robert Bigwood's current known residential address is: 13 Salvatore Cir, Swedesboro, NJ 08085. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Robert Bigwood?

Previous addresses associated with Robert Bigwood include: 50 Club House Rd, Key Largo, FL 33037; 97 W Shore Dr, Ashburnham, MA 01430; 818 Saint Andrews Dr, Wilmington, NC 28412; 3045 Overlook Dr, Hillsboro, OR 97124; 307 5Th, Clinton, IA 52732. Remember that this information might not be complete or up-to-date.

Where does Robert Bigwood live?

Woolwich Twp, NJ is the place where Robert Bigwood currently lives.

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