Richard Deeley

In the United States, there are 25 individuals named Richard Deeley spread across 23 states, with the largest populations residing in California, Pennsylvania, Florida.

Last updated Jan 29, 2024

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Richard E Deeley , Age 75

Alpena, MI

Has lived in:: Alpena, MI; Lachine, MI; Detroit, MI; Westland, MI

Related to:: Kenia Trejo, 31; Carlos Trejo, 53; Frank Sparks, 66; Eric Willis, 43

Phone number:: 989-379-****; 734-778-****

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Richard M Deeley , Age 64

San Jose, CA

Also known as:: Michael R Deeley; Richard Deely; Deeley M Richard

Has lived in:: San Jose, CA; Mountain View, CA

Related to:: Thuong Nguyen; Nam Yung; M Deeley, 64; Oliver Deeley, 34

Phone number:: 408-270-****

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Richard A Deeley , Age 61

Arabi, LA

Also known as:: Richard W Deeley; Richard H Deeley; Dick Deeley; Rick Deeley

Has lived in:: Arabi, LA; Highland, CA; Thousand Oaks, CA; Simi Valley, CA

Related to:: Stacy Montelongo, 62; Hannah Deeley, 24; Margaret Deeley, 88; Cherise Deeley, 62

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Richard J Deeley , Age 38

Salineville, OH

Has lived in:: Salineville, OH

Related to:: Lorna Deeley, 85; R Deeley; William Deeley, 89; Craig Deeley, 64

Phone number:: 330-679-****; 330-679-****

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Richard A Deeley , Age 98

Simi Valley, CA

Also known as:: Richard D Deeley; Rita A Deeley; Richard A Deely

Has lived in:: Simi Valley, CA; Camarillo, CA; Lancaster, CA

Related to:: Jason Riggio, 51; Judith Deeley, 74; Lindsay Deeley, 32; Carl Deeley, 69

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Public information about Richard Deeley

Phones & Addresses

Name

Addresses

Phones

Richard E Deeley

16131 Wormer St, Detroit, MI 48219

313-255-7291

Richard E Deeley

34743 Fountain Blvd, Westland, MI 48185

734-427-9454

Richard A Deeley

908 Clear Sky Pl, Simi Valley, CA 93065

805-285-0816

Richard E Deeley

4074 Dann Rd, Alpena, MI 49707

989-379-2180, 989-379-7088

Richard F Deeley

4936 Hawthorne St, Philadelphia, PA 19124

215-288-5767

Richard Deeley

1629 Allengrove St, Philadelphia, PA 19124

Richard H Deeley

1240 Kings Way, Redlands, CA 92373

909-793-5146, 909-793-7286

Richard H Deeley

225 Blueberry Ln, Thousand Oaks, CA 91360

Publications

Us Patents

Method And System For Creating And Validating Low Level Description Of Electronic Design

US Patent:

6324678, Nov 27, 2001

Filed:

Aug 22, 1996

Appl. No.:

8/701727

Inventors:

Carlos Dangelo - Los Gatos CA
Richard Deeley - San Jose CA
Vijay Nagasamy - Union City CA
Manoucher Vafai - Los Gatos CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1750

US Classification:

716 18

Abstract:

A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized.

High-Speed Internal Interconnection Technique For Integrated Circuits That Reduces The Number Of Signal Lines Through Multiplexing

US Patent:

5615126, Mar 25, 1997

Filed:

Aug 24, 1994

Appl. No.:

8/294973

Inventors:

Richard Deeley - San Jose CA
Carlos Dangelo - Los Gatos CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H02B 120

US Classification:

364489

Abstract:

Signal area efficiency in integrated circuit designs is improved by increasing the information efficiency of signal wiring on an integrated circuit. Candidate signals are selected for combination by prioritizing signals according to length of travel, travel path, and information content. Signals with low information content and with greater distance between endpoints make poor utilization of fixed wiring and provide the best candidates for improvement. Candidate signals which travel similar (substantially parallel) paths from point to point across the integrated circuit are combined to improve chip area utilization efficiency. A variety of techniques are described for combining low-information-content signals onto a small number of wires, transmitting them over the small number of wires, and re-expanding them at their destination. Assuming that the combining/expanding circuitry occupies less space than the point-to-point wiring which would otherwise be required, there is a net reduction in chip area. One aspect of the invention is directed to using auto-routing switching techniques for combining signals.

Integrated Multimedia System With Local Processor, Data Transfer Switch, Processing Modules, Fixed Functional Unit, Data Streamer, Interface Unit And Multiplexer, All Integrated On Multimedia Processor

US Patent:

6347344, Feb 12, 2002

Filed:

Oct 14, 1998

Appl. No.:

09/172286

Inventors:

David Baker - Chapel Hill NC
Christopher Basoglu - Bothell WA
Benjamin Cutler - Seattle WA
Richard Deeley - San Jose CA
Gregorio Gervasio - Sunnyvale CA
Atsuo Kawaguchi - San Jose CA
Keiji Kojima - Sagamihara, JP
Woobin Lee - Lynnwood WA
Takeshi Miyazaki - Tokyo, JP
Yatin Mundkur - Sunnyvale CA
Vinay Naik - Austin TX
Kiyokazu Nishioka - Odawara, JP
Toru Nojiri - Tokyo, JP
John ODonnell - Seattle WA
Sarang Padalkar - San Jose CA

Assignee:

Hitachi, Ltd. - Tokyo
Equator Technologies, Inc. - Campbell CA

International Classification:

G06F 300

US Classification:

710 20, 710 7, 712 32, 712 34, 712 36, 345501, 345502, 345503, 345504, 345519

Abstract:

An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A multiplexer is coupled to the interface unit and provides access between a selected number of I/O device driver units and external I/O devices via output pins.

Separable Cells Having Wiring Channels For Routing Signals Between Surrounding Cells

US Patent:

5905655, May 18, 1999

Filed:

Jun 9, 1997

Appl. No.:

8/871212

Inventors:

Richard Deeley - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F17/50

US Classification:

364491

Abstract:

On integrated circuit designs employing large, pre-defined circuit blocks, chip area utilization and signal routing is improved by permitting signals between circuit blocks surrounding (e. g. , on opposite sides of) a large circuit block (megacell) to physically pass through the megacell. The megacell is laid out so that a "parting line" is defined through the megacell. Circuits within the megacell are laid out so that no circuit "straddles" the parting line. The megacell can then be split or stretched about the parting line to create a wiring channel. The wiring channel is used for routing signals from the surrounding cells (circuit blocks) through the large circuit block (megacell). Signals between the separated portions of the stretched or split megacell on opposite sides of the parting line may be routed in one metal layer, while connections of surrounding cells through the megacell may be routed in another metal layer. A maximum split or stretch distance is defined for which the megacell performance specifications (e. g.

Method And System For Creating And Validating Low Level Description Of Electronic Design From Higher Level, Behavior-Oriented Description, Using Milestone Matrix Incorporated Into User-Interface

US Patent:

5553002, Sep 3, 1996

Filed:

Jun 14, 1993

Appl. No.:

8/077403

Inventors:

Carlos Dangelo - Los Gatos CA
Richard Deeley - San Jose CA
Vijay Nagasamy - Union City CA
Manoucher Vafai - Los Gatos CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1750

US Classification:

364489

Abstract:

A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications using a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized.

Processing Circuit And Method For Variable-Length Coding And Decoding

US Patent:

6507293, Jan 14, 2003

Filed:

Dec 21, 2000

Appl. No.:

09/750383

Inventors:

Richard M. Deeley - San Jose CA
Yatin Mundkur - Los Altos Hills CA
Woobin Lee - Lynnwood WA

Assignee:

Equator Technologies, Inc. - Campbell CA

International Classification:

H03M 740

US Classification:

341 67, 341 65

Abstract:

A variable-length encode/decode processor includes a central processing unit and an instruction buffer and a getbits processing engine coupled to the central processing unit. Such a processor can be used to encode data as variable-length symbols or to decode variable-length symbols such as those found in an MPEG bitstream.

Integrated Circuit Device Having A Switched Routing Network

US Patent:

5898677, Apr 27, 1999

Filed:

Jan 13, 1997

Appl. No.:

8/782585

Inventors:

Richard Deeley - San Jose CA
Carlos Dangelo - Los Gatos CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2900

US Classification:

370276

Abstract:

Separable Cells Having Wiring Channels For Routing Signals Between Surrounding Cells

US Patent:

5638288, Jun 10, 1997

Filed:

Aug 24, 1994

Appl. No.:

8/295094

Inventors:

Richard Deeley - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1750
H01L 2102

US Classification:

364489

Abstract:

Videos & Images

What are Richard Deeley's alternative names?

Known alternative names for Richard Deeley are: Angie Jones, Christina Jones, Kenia Trejo, Carlos Trejo, Frank Sparks, Eric Willis, Linda Barron. These can be aliases, maiden names, or nicknames.

What is Richard Deeley's current residential address?

Richard Deeley's current known residential address is: 4074 Dann Rd, Alpena, MI 49707. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Richard Deeley?

Previous addresses associated with Richard Deeley include: 1629 Allengrove St, Philadelphia, PA 19124; 3410 N Arrowhead Blvd, Blythe, CA 92225; 1986 Candle Pine Ln, Simi Valley, CA 93065; 300 Arneill, Camarillo, CA 93010; 34135 Village 34, Camarillo, CA 93012. Remember that this information might not be complete or up-to-date.

Where does Richard Deeley live?

Alpena, MI is the place where Richard Deeley currently lives.

How old is Richard Deeley?

Richard Deeley is 75 years old.

What is Richard Deeley date of birth?

Richard Deeley was born on 1949.

What is Richard Deeley's email?

Possible Relatives

David Deeley George Deeley James Deeley Joan Deeley John Deeley Kevin Deeley Lisa Deeley Richard Last Richard Stamps Richard Stan

Name Variants	Dick Deeley	Rick Deeley	Ricky Deeley
Ages	38 to 98
Phones	805-285-0816	760-544-7001	805-987-8901
Addresses	908 Clear Sky Pl, Simi Valley, CA 93065	1629 Allengrove St, Philadelphia, PA 19124	3410 N Arrowhead Blvd, Blythe, CA 92225
Business records	Product Sales Executive-Siemens Molecular Imaging / Siemens Healthcare	Software Engineer at Fico / Fico	President / R. A. DEELEY, D.D.S., PROFESSIONAL DENTAL CORP

Richard Deeley

What do we know about Richard Deeley

Public information about Richard Deeley

Phones & Addresses

Publications

Us Patents

Method And System For Creating And Validating Low Level Description Of Electronic Design

High-Speed Internal Interconnection Technique For Integrated Circuits That Reduces The Number Of Signal Lines Through Multiplexing

Integrated Multimedia System With Local Processor, Data Transfer Switch, Processing Modules, Fixed Functional Unit, Data Streamer, Interface Unit And Multiplexer, All Integrated On Multimedia Processor

Separable Cells Having Wiring Channels For Routing Signals Between Surrounding Cells

Method And System For Creating And Validating Low Level Description Of Electronic Design From Higher Level, Behavior-Oriented Description, Using Milestone Matrix Incorporated Into User-Interface

Processing Circuit And Method For Variable-Length Coding And Decoding

Integrated Circuit Device Having A Switched Routing Network

Separable Cells Having Wiring Channels For Routing Signals Between Surrounding Cells

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