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Paul Farrar

In the United States, there are 175 individuals named Paul Farrar spread across 41 states, with the largest populations residing in California, North Carolina, Florida. These Paul Farrar range in age from 42 to 86 years old. Some potential relatives include Chasity Farrar, Veronica Bueno, Michael Farrar. You can reach Paul Farrar through various email addresses, including paul.far***@gmail.com, paul.far***@netscape.net, boxxer1lov***@altavista.com. The associated phone number is 440-944-3773, along with 6 other potential numbers in the area codes corresponding to 703, 931, 510. For a comprehensive view, you can access contact details, phone numbers, addresses, emails, social media profiles, arrest records, photos, videos, public records, business records, resumes, CVs, work history, and related names to ensure you have all the information you need.

Public information about Paul Farrar

Resumes

Resumes

Director, Federal Public Safety Business Development At Thales Communications, Inc.

Paul Farrar Photo 1
Position:
Director, Federal Public Safety Business Development at Thales Communications, Inc.
Location:
Washington D.C. Metro Area
Industry:
Defense & Space
Work:
Thales Communications, Inc.
Director, Federal Public Safety Business Development Rhode and Schwarz 2012 - 2012
Program Manager

Vp At Ibm

Paul Farrar Photo 2
Location:
Greater New York City Area
Industry:
Semiconductors

Coordinator, Tobacco Region Scholarship At Southwest Virginia Higher Education Center

Paul Farrar Photo 3
Position:
Coordinator, Tobacco Region Scholarship Southside at Southwest Virginia Higher Education Center
Location:
Greensboro/Winston-Salem, North Carolina Area
Industry:
Higher Education
Work:
Southwest Virginia Higher Education Center - South Boston, VA since Jan 2009
Coordinator, Tobacco Region Scholarship Southside Southwest Virginia Higher Education Center Jan 2009 - May 2012
Southside Tobacco Loan Forgiveness Program Coordinator Institute for Advanced Learning and Research Jan 2008 - Jan 2009
Academic Outreach Coordinator Martinsville City Public Schools Aug 2004 - Jan 2008
Civics/Economics Teacher
Education:
Averett University 2003 - 2004
Master, Education Averett University 2001 - 2003
Bachelor, Criminal Justice/Sociology Patrick Henry Community College 1999 - 2001
Associate, Administration of Justice
Interests:
Marketing strategies, Higher Education, History, Politics
Honor & Awards:
Elected Representative At Large for VASFAA (Virginia Association of Student Financial Aid Administrators) Honored as a 2012 Distinguished Patrick Henry Alumni, by the Patrick Henry Community College Foundation. http://phccblog.com/2012/05/...

Paul Farrar

Paul Farrar Photo 4
Location:
United States

Paul Farrar - Hagerstown, MD

Paul Farrar Photo 5
Work:
OHL/Walmart.com - Chambersburg, PA Aug 2014 to Feb 2015
Receiving Lead DOT Foods May 2011 to Jun 2013
General Laborer Self employed Apr 2010 to Mar 2011
General Laborer Pepsi PBG/Manpower - Williamsport, MD Jul 2009 to Feb 2010
Warehouse Associate Home Depot Direct - Hagerstown, MD Feb 2005 to Nov 2008
Warehouse Associate Janitorial - Hagerstown, MD Oct 2004 to Jan 2005
General Contractor Rick Galloway - Hagerstown, MD Apr 2002 to Oct 2004
Drywall Technician Colby Floors - Hagerstown, MD Feb 2002 to Apr 2002
Flooring Installer Craig Dagenhart Mar 2001 to Feb 2002
Carpenters Helper

General Manager At The Timbers

Paul Farrar Photo 6
Position:
General manager at the timbers
Location:
Fort Myers, Florida Area
Industry:
Food & Beverages
Work:
The timbers
general manager Hyatt Coconut Plantation Resort 2003 - 2008
Food and Beverave Manager

Paul Farrar - Spencer, VA

Paul Farrar Photo 7
Work:
Southwest Virginia Higher Education Center 2009 to 2000
Southside Tobacco Loan Forgiveness Coordinator Institute For Advanced Learning and Research - Danville, VA 2008 to 2009
Eighth Grade Civics Teacher, 2004 to 2008
Education:
Averett University 2004
Master of Education in History Averett University 2002
B.S. in Criminal Justice/Sociology Patrick Henry Community College 1999
A.S. in Administration of Justice

Paul Farrar

Paul Farrar Photo 8
Location:
Greater Detroit Area
Industry:
Automotive
Background search with BeenVerified
Data provided by Veripages

Phones & Addresses

Name
Addresses
Phones
Paul F Farrar
318-368-8475, 318-368-2087, 318-368-1430
Paul Farrar
610-372-3058
Paul H Farrar
440-944-3773
Paul Farrar
215-226-0931
Paul Farrar
541-899-0143
Paul F Farrar
703-729-3089, 703-729-1269
Paul Farrar
610-372-3058
Paul Farrar
843-785-7250, 843-842-2048

Business Records

Name / Title
Company / Classification
Phones & Addresses
Paul S. Farrar
Principal
Pauls Lawn Care
Lawn/Garden Services
2673 Tom Sawyer Rd, Muscatine, IA 52761
Paul Farrar
Purchasing Director
Johnson Marcraft Inc
Mechanical or Industrial Engineering · Business Association Mfg Blowers/Fans · Business Association Mfg Blowers/Fans Mfg Refrigeration/Heating Equipment · Ac, Refrigeration, & Forced Air Heating · Refrigeration and Heating Equipment · Air Conditioning/Htg/Refrig Eq · Plumbing, Heating, Air-conditioning
11880 Dorsett Rd, Maryland Heights, MO 63043
314-739-0037, 314-739-1556
Paul Farrar
Budget Alarm
Burglar Alarm Systems - Dealers. Monitoring & Service
2510 Wentworth Dr, South San Francisco, CA 94080
650-583-9359
Paul Farrar
Sales And Marketing Executive
Mount Airy Electric, LLC
Electrical Contractor
7403 Westvale Ct, Mount Airy, MD 21771
301-831-7170
Paul Farrar
Paul Farrar Tree Service
Tree Service
175 Prospect St, Biddeford, ME 04101
207-775-2159
Paul Farrar
Owner
Farrar Construction
Farrar Inc
Contractors - General
175 Wild Goose Ln, Roseburg, OR 97470
541-496-4564
Paul Farrar
President
Vista Teachers Association Scholarship Fund
Professional Organization
PO Box 1302, Vista, CA 92085
1717 E Vis Way, Vista, CA 92084
Paul H. Farrar
Director
AFC ENTERPRISES, INC
San Antonio, TX 78201

Publications

Us Patents

Damascene Structure And Method Of Making

US Patent:
6451683, Sep 17, 2002
Filed:
Aug 28, 2000
Appl. No.:
09/648465
Inventors:
Paul A. Farrar - South Burlington VT
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2906
US Classification:
438622, 438623, 438638
Abstract:
A damascene structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The selected low dielectric constant materials have similar methods of formation and similar capacities to withstand physical and thermal stress. In addition, the etchant used for each low dielectric constant insulating layer has a very small etching rate relative to the other low dielectric constant insulating layers. Thus, the low dielectric constant materials act as insulating layers through which trenches and vias are formed.

Low Capacitance Wiring Layout And Method For Making Same

US Patent:
6475899, Nov 5, 2002
Filed:
Oct 17, 2001
Appl. No.:
09/978071
Inventors:
Paul A. Farrar - South Burlington VT
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 214763
US Classification:
438622, 438624, 438666
Abstract:
Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated circuits have at least two planes of wiring adjacent to each other and extending in the same direction. One embodiment may further include a larger than normal insulator material between planes of wiring extending in one direction and at least one plane of wiring extending in a second direction transverse to the first direction. Each of the wiring channels in a wiring plane may be offset relative to a respective wiring channel in the next adjacent wiring plane which extends in the same direction.

Reduced Power Dram Device And Method

US Patent:
6356500, Mar 12, 2002
Filed:
Aug 23, 2000
Appl. No.:
09/643945
Inventors:
Eugene H. Cloud - Boise ID
Kie Y. Ahn - Chappaqua NY
Leonard Forbes - Corvallis OR
Paul A. Farrar - Corvallis OR
Kevin G. Donohoe - Boise ID
Alan R. Reinberg - Westport CT
David J. Mcelroy - Livingston TX
Luan C. Tran - Meridian ID
Joseph Geusic - Berkeley Heights NJ
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365226, 36523001, 365240
Abstract:
A memory device and method employing a scheme for reduced power consumption is disclosed. By dividing a memory array sector into memory sub arrays, the memory device can provide power to memory sub arrays that need to be powered up or, in the alternative, powered down. This reduces the power consumption and heat generation associated with high speed and high capacity memory devices.

Conductive Implant Structure In A Dielectric

US Patent:
6495919, Dec 17, 2002
Filed:
Jun 26, 2001
Appl. No.:
09/892162
Inventors:
Paul A. Farrar - South Burlington VT
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2348
US Classification:
257759, 257758, 257760
Abstract:
The present invention is directed toward the formation of implanted thermally and electrically conductive structures in a dielectric. An electrically conductive structure, such as an interconnect, is formed through ion implantation into several levels within a dielectric layer to penetrate into an electrically conductive region beneath the dielectric layer, such as a semiconductor substrate. Ion implantation continues in discreet, overlapping implantations of the ions from the electrical conductive region up to the top of the dielectric layer so as to form a continuous interconnect. Structural qualities achieved by the method of the present invention include a low interconnect-conductive region resistivity and a low thermal-cycle stress between the interconnect and the dielectric layer in which the interconnect has been implanted. Implantation elements are selected in connection with dielectric materials so that heat treatment will cause continuous metallic structures to form within the interconnect implantation area. In an alternative embodiment, implantation dosages and depths are selected to form a thermally conductive structure that is entirely insulated within the dielectric layer and that function as a conduit to heat-sink structures.

Etch Stop In Damascene Interconnect Structure And Method Of Making

US Patent:
6509258, Jan 21, 2003
Filed:
Aug 30, 2001
Appl. No.:
09/941762
Inventors:
Paul A. Farrar - South Burlington VT
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 214763
US Classification:
438622, 438638
Abstract:
An interconnect structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The low dielectric constant materials act as insulating layers through which trenches and vias are subsequently formed by employing a timed etching. Since the low dielectric constant materials are selected so that the etchant available for each one has only a small etch rate relative to the other low dielectric constant materials, the plurality of low dielectric constant materials act as etch stops during the fabrication of interconnect structures. This way, the etch stop layers employed in the prior art are eliminated and the number of fabrication steps is reduced.

Method Of Forming Buried Conductor Patterns By Surface Transformation Of Empty Spaces In Solid State Materials

US Patent:
6383924, May 7, 2002
Filed:
Dec 13, 2000
Appl. No.:
09/734547
Inventors:
Paul A. Farrar - South Burlington VT
Joseph Geusic - Berkeley Heights NJ
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2144
US Classification:
438667, 438589, 438620, 438977, 438967, 438705, 438795
Abstract:
A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the monocrystalline substrate and annealing the monocrystalline substrate to form empty-spaced patterns of various geometries. The empty-spaced patterns are then connected through vias with surfaces of the monocrystalline substrate. The empty-spaced patterns and their respective vias are subsequently filled with conductive materials.

Subtractive Metallization Structure With Low Dielectric Constant Insulating Layers

US Patent:
6522008, Feb 18, 2003
Filed:
Nov 26, 2001
Appl. No.:
09/991666
Inventors:
Paul A. Farrar - South Burlington VT
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2348
US Classification:
257758, 438622, 438623, 257759
Abstract:
A subtractive metallization structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The selected low dielectric constant materials have similar methods of formation and similar capacities to withstand physical and thermal stress. In addition, the etchant used for each low dielectric constant insulating layer has a very small etching rate relative to the other low dielectric constant insulating layers.

Low Capacitance Wiring Layout And Method For Making Same

US Patent:
6522011, Feb 18, 2003
Filed:
Aug 15, 2000
Appl. No.:
09/638390
Inventors:
Paul A. Farrar - South Burlington VT
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2348
US Classification:
257773, 257758, 257776
Abstract:
Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated circuits have at least two planes of wiring adjacent to each other and extending in the same direction. One embodiment may further include a larger than normal insulator material between planes of wiring extending in one direction and at least one plane of wiring extending in a second direction transverse to the first direction. Each of the wiring channels in a wiring plane may be offset relative to a respective wiring channel in the next adjacent wiring plane which extends in the same direction.

FAQ: Learn more about Paul Farrar

What are Paul Farrar's alternative names?

Known alternative names for Paul Farrar are: John Miller, Lynda Miller, Patricia Miller, Susanne Miller, Bobby West, Jessica Gill. These can be aliases, maiden names, or nicknames.

What is Paul Farrar's current residential address?

Paul Farrar's current known residential address is: 8926 Western Pines Dr, Douglasville, GA 30134. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Paul Farrar?

Previous addresses associated with Paul Farrar include: 22478 Pine Ridge, Ashburn, VA 20148; 31701 Eddy, Willoughby, OH 44094; 1010 Bagley, Fayetteville, TN 37334; 40 Sheffield Ct, San Pablo, CA 94806; 15185 Stillfield Pl, Centreville, VA 20120. Remember that this information might not be complete or up-to-date.

Where does Paul Farrar live?

Douglasville, GA is the place where Paul Farrar currently lives.

How old is Paul Farrar?

Paul Farrar is 65 years old.

What is Paul Farrar date of birth?

Paul Farrar was born on 1959.

What is Paul Farrar's email?

Paul Farrar has such email addresses: paul.far***@gmail.com, paul.far***@netscape.net, boxxer1lov***@altavista.com, tzone1***@angelfire.com, major.john***@yahoo.com, paulfar***@att.net. Note that the accuracy of these emails may vary and they are subject to privacy laws and restrictions.

What is Paul Farrar's telephone number?

Paul Farrar's known telephone numbers are: 440-944-3773, 703-729-3089, 703-729-1269, 931-433-5146, 510-237-8940, 703-222-8630. However, these numbers are subject to change and privacy restrictions.

Who is Paul Farrar related to?

Known relatives of Paul Farrar are: John Miller, Lynda Miller, Patricia Miller, Susanne Miller, Bobby West, Jessica Gill. This information is based on available public records.

What are Paul Farrar's alternative names?

Known alternative names for Paul Farrar are: John Miller, Lynda Miller, Patricia Miller, Susanne Miller, Bobby West, Jessica Gill. These can be aliases, maiden names, or nicknames.

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