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Hugo Chan

In the United States, there are 19 individuals named Hugo Chan spread across 18 states, with the largest populations residing in California, Georgia, Illinois. These Hugo Chan range in age from 39 to 77 years old. Some potential relatives include Jian Chen, Ling Chen, Ren Chen. You can reach Hugo Chan through their email address, which is hugo.c***@worldnet.att.net. The associated phone number is 408-807-3823, along with 5 other potential numbers in the area codes corresponding to 530, 612, 405. For a comprehensive view, you can access contact details, phone numbers, addresses, emails, social media profiles, arrest records, photos, videos, public records, business records, resumes, CVs, work history, and related names to ensure you have all the information you need.

Public information about Hugo Chan

Resumes

Resumes

Hugo Chan

Hugo Chan Photo 1
Location:
New York, NY
Industry:
Investment Management
Work:
Hku Mba (Faculty of Business and Economics, the University of Hong Kong) 2013 - 2014
Mba

Cutting Room And Sample Room Manager

Hugo Chan Photo 2
Work:
Rubin Singer
Cutting Room and Sample Room Manager
Education:
Fashion Institute of Technology 2006 - 2010

Sandwich Artist

Hugo Chan Photo 3
Location:
Los Angeles, CA
Industry:
Restaurants
Work:
Kimarya Enterprises Mar 2013 - Apr 2013
Sandwich Artist Kimarya Entrprises 2013 - 2013
Sandwich Artist
Education:
Lamar High School, Houston, Texas 2005 - 2009
Skills:
Assistants, Inventory Management, Inventory Analysis, Restaurants, Customer Service, Cashiering, Assistant Work
Languages:
English
Spanish

Hugo Chan

Hugo Chan Photo 4
Location:
San Francisco, CA
Industry:
Investment Banking

Hugo Chan

Hugo Chan Photo 5

Vp, Implantable Medical Devices

Hugo Chan Photo 6
Location:
670 north Mccarthy Blvd, Milpitas, CA 95035
Industry:
Medical Devices
Work:
Ami
Vp, Implantable Medical Devices
Education:
University of California, Berkeley 1971 - 1977

Hugo Chan

Hugo Chan Photo 7
Location:
United States

Hugo Perez Chan - Compton, CA

Hugo Chan Photo 8
Work:
Budget Mobile Oct 2014 to 2000
Mobile Sales Associate
Education:
Los Angeles City College - Los Angeles, CA 2014 to 2018
Math

Publications

Us Patents

Multi-State Josephson Memory

US Patent:
5872731, Feb 16, 1999
Filed:
Oct 10, 1997
Appl. No.:
8/948570
Inventors:
Hugo W-K. Chan - Rancho Palos Verdes CA
Arnold H. Silver - Rancho Palos Verdes CA
Robert D. Sandell - Manhattan Beach CA
Assignee:
TRW Inc. - Redondo Beach CA
International Classification:
G11C 1144
US Classification:
365162
Abstract:
A multi-state Josephson memory in a superconductor integrated circuit includes a plurality of superconductive quantum interference device (SQUID) memory cells 2 each having a SQUID 4 characterized by a SQUID loop inductance L and a junction critical current I. sub. c, which determine the number of memory states that can be stored in the SQUID 4. A gate current I. sub. g is transmitted to the superconductive inductors 6 and 8 of the SQUID 4 to perform a read operation by crossing a designated number of current threshold boundaries corresponding to the memory state stored in the SQUID, so that the Josephson junction 12 of the SQUID 4 generates a number of pulses corresponding to the memory state. A control current I. sub. con writes data to the SQUID 4 through a control current input 16, and is preferably magnetically coupled to the SQUID 4 through superconductive inductor pairs 18, 6 and 20, 8.

High-Temperature Ssns And Sns Josephson Junction And Method Of Making Junction

US Patent:
5892243, Apr 6, 1999
Filed:
Dec 6, 1996
Appl. No.:
8/761412
Inventors:
Hugo W. Chan - Palos Verdes Estates CA
Assignee:
TRW Inc. - Redondo Beach CA
International Classification:
H01L 2906
US Classification:
257 31
Abstract:
A high temperature superconductor junction and a method of forming the junction are disclosed. The junction 40 comprises a first high-T. sub. c, superconductive layer (first base electrode layer) 46 on a substrate 42 and a dielectric layer 48 on the first high-T. sub. c, superconductive layer. The dielectric layer and the first high-T. sub. c superconductive layer define a ramp edge 50. A trilayer SNS structure 52 is disposed on the ramp edge to form an SSNS junction. The SNS structure comprises a second high-T. sub. c, superconductive layer (second base electrode layer) 54 directly on the first high-T. sub. c superconductive layer, a normal barrier layer 56 on the second high-T. sub. c superconductive layer, and a third high-T. sub. c superconductive layer 58 (counterelectrode) on the barrier layer.

Implant-Patterned Superconductive Device And A Method For Indirect Ion Implantation Of Superconductive Films

US Patent:
6335108, Jan 1, 2002
Filed:
Sep 7, 2000
Appl. No.:
09/657203
Inventors:
John R. LaGraff - Niskayuna NY
James M. Murduck - Redondo Beach CA
Hugo W-K. Chan - Fremont CA
Assignee:
TRW Inc. - Redondo Beach CA
International Classification:
H01L 3924
US Classification:
428689, 505238, 505325, 428699, 428701, 428702, 428930
Abstract:
An implant patterned superconductive device and a method for indirect implant-patterning of oxide superconducting materials is provided. The method forms a device having an oxide superconducting layer on a substrate, deposits a passivation layer atop the oxide superconducting layer, and implants chemical impurities in a selected portion of the superconducting layer through the passivation layer. This modifies the conductivity of the selected portion of the oxide superconducting layer and electrically isolates the selected portion from the non-selected portion of the oxide superconducting layer. The passivation layer is made of a material less susceptible to implant damage than the oxide superconducting layer to allow inhibition of the oxide superconducting layer while protecting the crystalline structure of the top surface of the oxide superconducting layer and keeping it planarized. The passivation layer is preferably a dielectric material having a crystal lattice structure which is compatible to that of the oxide superconducting layer. The method is especially efficient for the fabrication of devices with multiple layers of oxide superconductive materials because it does not degrade the epitaxial templates crystalline structure.

Method For Indirect Ion Implantation Of Oxide Superconductive Films

US Patent:
6147032, Nov 14, 2000
Filed:
May 19, 1999
Appl. No.:
9/314772
Inventors:
John R. LaGraff - Niskayuna NY
James M. Murduck - Redondo Beach CA
Hugo W-K. Chan - Fremont CA
Assignee:
TRW Inc. - Redondo Beach CA
International Classification:
H01L 3924
US Classification:
505325
Abstract:
An implant patterned superconductive device and a method for indirect implant-patterning of oxide superconducting materials is provided. The method forms a device having an oxide superconducting layer on a substrate, deposits a passivation layer atop the oxide superconducting layer, and implants chemical impurities in a selected portion of the superconducting layer through the passivation layer. This modifies the conductivity of the selected portion of the oxide superconducting layer and electrically isolates the selected portion from the non-selected portion of the oxide superconducting layer. The passivation layer is made of a material less susceptible to implant damage than the oxide superconducting layer to allow inhibition of the oxide superconducting layer while protecting the crystalline structure of the top surface of the oxide superconducting layer and keeping it planarized. The passivation layer is preferably a dielectric material having a crystal lattice structure which is compatible to that of the oxide superconducting layer. The method is especially efficient for the fabrication of devices with multiple layers of oxide superconductive materials because it does not degrade the epitaxial template's crystalline structure.

High-Speed Gamma Pulse Suppression Circuit For Semiconductor Infrared Detectors

US Patent:
5436451, Jul 25, 1995
Filed:
Feb 2, 1993
Appl. No.:
8/019391
Inventors:
Arnold H. Silver - Rancho Palos Verdes CA
Hugo W.-K. Chan - Rancho Palos Verdes CA
Assignee:
TRW Inc. - Redondo Beach CA
International Classification:
H01L 3922
H04B 110
G01J 500
US Classification:
2503361
Abstract:
A high-speed gamma pulse suppression circuit employing a frequency discrimination and sampling technique for elimination of gamma induced noise from semiconductor infrared detectors. The gamma pulse suppression circuit includes a high pass filter for separating high-frequency gamma induced pulses from a detector signal and a gamma pulse detector for detecting the gamma induced pulses. The gamma pulse suppression circuit is connected in parallel with a detector readout circuit such that the suppression circuit causes the readout circuit to discard samples of the detector signal in which gamma induced pulses are detected. The gamma pulse suppression circuit provides effective and efficient real time gamma pulse suppression by completely eliminating the detected gamma pulses from the detector signal, while preserving the quality of the signal.

Planar In-Line Resistors For Superconductor Circuits

US Patent:
5912503, Jun 15, 1999
Filed:
Jan 2, 1997
Appl. No.:
8/785031
Inventors:
Hugo W. Chan - Rancho Palos Verdes CA
Arnold H. Silver - Rancho Palos Verdes CA
Assignee:
TRW Inc. - Redondo Beach CA
International Classification:
H01L 3900
H01B 1200
B32B 1200
US Classification:
257663
Abstract:
A method of fabricating a low-inductance, in-line resistor includes the steps of: depositing a superconductive layer 12 on a base layer 14; patterning an interconnect region 16 on the superconductive layer 12; and converting the interconnect region 16 of the superconductive layer 12 to a resistor material region 18. The resistor region 18 and the superconductive layer 12 are substantially in the same plane. The method can further include the steps of depositing a conductive layer 22 on the resistor region 18 and on the photo-resist layer 20, and lifting off the photo-resist layer 20 to leave the conductive layer 22 on the resistor region 18. As such, the conductive layer 22 provides a low sheet resistivity for the resistor region 18. In another embodiment, the method includes the steps of: depositing in-situ a superconductive layer 12 on a base layer 14; depositing in-situ a conductive layer 22 on the superconductive layer 12 to form a bi-layer 24; patterning an interconnect region 16 on the bi-layer 24; and converting the interconnect region 16 of the bi-layer 24 to a resistor material region 18.

Superconductive Quantum Interference Device For Digital Logic Circuits

US Patent:
5863868, Jan 26, 1999
Filed:
Sep 25, 1997
Appl. No.:
8/937372
Inventors:
Hugo Wai-Kung Chan - Rancho Palos Verdes CA
Kenneth P. Daly - Rancho Palos Verdes CA
James M. Murduck - Redondo Beach CA
Assignee:
TRW Inc. - Redondo Beach CA
International Classification:
G01B 3900
H01L 2906
H01L 3922
G01P 3900
US Classification:
505162
Abstract:
A SQUID 10 was multiple junctions, each junction allowing a critical current to flow therethrough. The SQUID 10 comprises a laminar structure including: (a) a substantially planar substrate 12; (b) a first high temperature superconductive layer 14 of substantially uniform thickness deposited on the substrates; (c) a dielectric layer 16 deposited on the first superconductive layer 14, the dielectric layer 16 comprising a planar level segment 18 having two ramp segments defining SQUID junctions at opposing ends 20 and defining SQUID hole; and (d) a second high temperature superconductive layer 24 of substantially uniform thickness deposited on the dielectric layer 16, the second high temperature superconductive layer 24 covering all three segments of the dielectric layer 16. A magnetic field substantially parallel to the substrate applied to the SQUID hole modulates a critical current flowing through the junctions while minimizing magnetic field penetration into the junctions and minimizing SQUID loop inductance.

Submicron Josephson Junction And Method For Its Fabrication

US Patent:
5286336, Feb 15, 1994
Filed:
Nov 2, 1992
Appl. No.:
7/952011
Inventors:
Hugo W. Chan - Rancho Palos Verdes CA
Arnold H. Silver - Rancho Palos Verdes CA
Robert D. Sandell - Manhattan Beach CA
James M. Murduck - Lawndale CA
Assignee:
TRW Inc. - Redondo Beach CA
International Classification:
B44C 122
C03C 1500
C03C 2506
C23F 100
US Classification:
156643
Abstract:
A Josephson junction and a method for its fabrication in which a laminated junction layer is formed in situ on the side edge of a base electrode contact. The laminated junction layer forms the Josephson junction of the present invention and includes an insulating or barrier layer sandwiched between a superconducting base electrode and a superconducting counter electrode. The Josephson junction is formed on the side edge of the base electrode contact to allow very small junction areas to be fabricated using conventional optical lithographic techniques, such as photolithography. The laminated junction layer is formed in situ, with the three layers of the laminated junction layer being formed successively without removing the device from the controlled atmosphere of the deposition system, to prevent contamination of the junction region.

FAQ: Learn more about Hugo Chan

What is Hugo Chan's telephone number?

Hugo Chan's known telephone numbers are: 408-807-3823, 530-713-2785, 530-671-6148, 612-353-4084, 405-751-5501, 510-668-1836. However, these numbers are subject to change and privacy restrictions.

How is Hugo Chan also known?

Hugo Chan is also known as: Hugo T Chan, Hugo C Chan, Hugo H Chan, Hugo D Chan, N Chan, Hugo Cchan, Hugo C Shieh. These names can be aliases, nicknames, or other names they have used.

Who is Hugo Chan related to?

Known relatives of Hugo Chan are: Ling Yuen, Hugo Chan, Ying Chan, Yuen Chan, Andrew Chan, Stanley Chiu, Vanessa Chiu. This information is based on available public records.

What are Hugo Chan's alternative names?

Known alternative names for Hugo Chan are: Ling Yuen, Hugo Chan, Ying Chan, Yuen Chan, Andrew Chan, Stanley Chiu, Vanessa Chiu. These can be aliases, maiden names, or nicknames.

What is Hugo Chan's current residential address?

Hugo Chan's current known residential address is: 1215 Plumas St Ste 1200, Yuba City, CA 95991. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Hugo Chan?

Previous addresses associated with Hugo Chan include: 46850 Sentinel Dr, Fremont, CA 94539; 28 Spy Glass Hl, Oakland, CA 94618; 2331 Whitestone Expy, Whitestone, NY 11357; 2390 Travis Pines Dr, Augusta, GA 30906; 306 N 69Th Ave, West Richland, WA 99353. Remember that this information might not be complete or up-to-date.

Where does Hugo Chan live?

Yuba City, CA is the place where Hugo Chan currently lives.

How old is Hugo Chan?

Hugo Chan is 77 years old.

What is Hugo Chan date of birth?

Hugo Chan was born on 1946.

What is the main specialties of Hugo Chan?

Hugo is a Obstetrics & Gynecology

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