Chung Lam

475 individuals named Chung Lam found in 44 states. Most people reside in California, New York, Pennsylvania.

Public information about Chung Lam

Resumes

Chung F Lam

Location:

San Jose, CA

Industry:

Telecommunications

Work:

Varian Medical Systems Mar 2014 - Feb 2020
Senior Reliability Engineer Emcore Corporation Oct 2008 - Jan 2014
Senior Manager, Quality and Reliability Avanex Nov 2007 - Oct 2008
Reliability Manager, Ams Business Unit Mobileaccess Networks Aug 2005 - Jul 2007
Reliability Engineering Supervisor Lightconnect Mar 2001 - May 2005
Manager of Reliability, Quality and Failure Analysis Read-Rite Corporation-Western Digital Aug 1995 - Mar 2001
Reliability Team Leader and Esd Program Manager Ibm Aug 1982 - Aug 1995
Staff Mechanical Engineer, Npi Program Manager

Education:

University of Washington 1979 - 1982
Master of Science, Masters, Mechanical Engineering Oregon State University 1977 - 1979
Bachelor of Science In Mechanical Engineering, Bachelors, Mechanical Engineering

Skills:

Design of Experiments, Testing, Fmea, Quality Management, Semiconductors, Product Lifecycle Management, Cross Functional Team Leadership, Engineering Management, Failure Analysis, Product Development, Supplier Quality, Minitab, Quality System, Telecommunications, Process Control, Electronics, Reliability Test, Engineering, Reliability Predition and Modeling, Npi Management, Failure Mode and Effects Analysis, Iso Audit and Certifications, Reliability Stress Testing, Process Capability Analysis, Product Certification, Process Capability, Six Sigma

Interests:

Basket Ball
Travel
Biking

Languages:

Mandarin
English

Owner

Location:

Kingston, NY

Industry:

Education Management

Work:

C Gourmet Restaurant
Owner

Human Resources Manager

Location:

San Francisco, CA

Industry:

Human Resources

Work:

Dome Cleaning, Inc. May 2017 - Nov 2018
Human Resources Advisor Dome Cleaning, Inc. May 2017 - Nov 2018
Human Resources Manager Dome Cleaning, Inc. Feb 2017 - May 2017
Human Resources Coordinator and Recruiter Apa Family Support Services Feb 2016 - Feb 2017
Bilingual Employment Program Assistant Chase 2014 - 2015
Bank Teller

Education:

University of California, Santa Cruz 2009 - 2014
Bachelors, Bachelor of Arts, Economics

Skills:

Microsoft Office, Customer Service, Powerpoint, Microsoft Word, Event Planning, Leadership, Foreign Languages, Microsoft Powerpoint

Languages:

English
French
Mandarin

Retail

Location:

Rosemead, CA

Industry:

Fine Art

Work:

Xx Sculptures
Retail

Technician

Location:

Union City, CA

Work:

Ttm Technologies
Technician

Expeditor, Sap

Location:

Grand Prairie, TX

Industry:

Warehousing

Work:

Coopertires
Expeditor, Sap Liberty National Life Insurance Company Feb 2014 - May 2014
Agent Syncreon Sep 2013 - Feb 2014
Safety and Security Marshall Syncreon Jun 2013 - Feb 2014
Logistics Coordinator

Education:

Ulster University

Skills:

Logistics, Management, Warehousing, Data Analysis, Team Building, Warehouse Management, Microsoft Excel, Supply Chain Management, Sap, Inventory Management, Supply Chain, Health and Safety, Inventory Control, Materials Management

John Mcdonogh Senior High School

Work:

John Mcdonogh Senior High School

Education:

John Mcdonogh Sr. High School

Principal Scientist Manager

Location:

Durham, NC

Industry:

Chemicals

Work:

Bayer Cropscience
Principal Scientist Manager

Skills:

Uv/Vis, Organic Chemistry, Chromatography, Organic Synthesis, Chemical Engineering, Sap, Chemistry, Analytical Chemistry, R&D, Crop Protection, Mass Spectrometry, Hplc, Gas Chromatography, Biochemistry, Agriculture, Science, Glp, Lifesciences, Nmr, Biotechnology, Agronomy, Polymers, Agribusiness, Molecular Biology, Life Sciences

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Phones & Addresses

Name

Addresses

Phones

Chung Tao Lam

Gloucester, NJ

856-931-2601

Chung Ting Lam

Clearwater, FL

727-585-9083

Chung Fai Lam

San Jose, CA

408-251-5330, 408-996-7608

Chung Wai Lam

Houston, TX

281-599-0631

Chung Wai Lam

Richmond, CA

510-234-6216

Chung Dock Lam

San Francisco, CA

415-397-9286, 415-681-5517

Chung Wai Lam

West Palm Beach, FL

561-304-3417

Chung H Lam

30 Crescent Rd, Westport, CT 06880

203-341-9888

Chung Lam

414 N Railroad Ave, Staten Island, NY 10304

Chung Lam

41105 Forley St #1, Flushing, NY 11373

Chung Lam

4757 Lehrer Dr, San Diego, CA 92117

858-490-6263

Chung Lam

5400 NW 39Th Ave, Gainesville, FL 32606

Chung Lam

548 60Th St, Brooklyn, NY 11220

Chung Lam

4441 Fandon Ave, El Monte, CA 91732

626-222-3331

Chung Lam

866 51St St, Brooklyn, NY 11220

Chung Lam

8633 Union Pl, Manassas, VA 20111

Business Records

Name / Title

Company / Classification

Phones & Addresses

Chung Man Lam
President

SOL MINISTRY CORP

28 Grenwold Rd 6179018111, Quincy, MA 02169
75 Farrington St #2, Quincy, MA 02170

Chung Lam
Principal

Empire Szechuan Smithtown
Eating Place

769 Middle Country Rd, Head of the Harbor, NY 11780

Chung Lam
Executive Office Administrator

American Institute of Chemical Engineers
Periodicals: Publishing, or Publishing and Pr...

3 Park Ave Fl 19, New York, NY 10016

Chung L. Lam
Principal

Renovalue Inc
Nonclassifiable Establishments

555 Main St, East Orange, NJ 07018

Chung W. Lam
Managing

Consummate Gourmet LLC
Grocery Store

491 El Camino Real, Millbrae, CA 94030

Chung Lam
executive officer

C Gourment Restaurant
Eating Places

907 Ulster Avenue, Kingston, NY 12401
Website: cgourmet4u.com

Chung Lam
Partner, executive officer, Founder, Owner

C Gourment Restaurant

907 Ulster Ave, Kingston, NY 12401
845-338-0033, 845-339-2828

Chung Man Lam
Secretary

SEED MUSIC AND ARTS CENTER INC

1458 Hancock St, Quincy, MA 02169
75 Farrington St Ap #2, Quincy, MA 02170

Publications

Us Patents

Fabricating A Square Spacer

US Patent:

6426524, Jul 30, 2002

Filed:

Oct 18, 2000

Appl. No.:

09/691547

Inventors:

Chung Hon Lam - Williston VT
Jed Hickory Rankin - Burlington VT
Christa Regina Willets - Jericho VT
Arthur Paul Johnson - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27108

US Classification:

257296, 257309, 257328, 257329, 257330, 257331, 257332, 438303, 438305

Abstract:

A square spacer and method of fabrication. The method includes forming a spacer film on a mandrel positioned on a substrate, forming an oxide film on the spacer film, performing a first etching, and performing a second etching. The spacer film is formed on perpendicular first and second sides of the mandrel. A first region and a second region of the spacer film are on the first side and the second side of the mandrel, respectively. The spacer film may include a conductive material such as polysilicon or tungsten. The spacer film may alternatively include an insulative material such as silicon dioxide, silicon nitride, or silicon oxynitride. The oxide film is formed such that a first region and a second region of the oxide film are on the first region and the second region of the spacer film, respectively. The oxide film may include silicon dioxide. The first etching etches away the first region of the oxide film and a portion of the first region of the spacer film.

Nvram Array Device With Enhanced Write And Erase

US Patent:

6445029, Sep 3, 2002

Filed:

Oct 24, 2000

Appl. No.:

09/695151

Inventors:

Chung H. Lam - Williston VT
Richard Q. Williams - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2976

US Classification:

257314, 257316, 257321, 257322, 438259, 438267, 438589

Abstract:

Increased write and erase tunnelling currents are developed by enhancement of an electric field near a floating gate with a shaped edge structure overlapping a source/drain diffusion and developing increased floating gate area with angled regions joined by edges in order to reduce write and erase cycle times. The edge structure is formed by selective and preferential etching in accordance with the crystal structure of a monocrystalline semiconductor substrate. The sharpness of the edges and concentration of the electric field may be enhanced by consumption and stress effects of oxidation of the substrate to form a floating gate insulator.

Antifuse Structure And Process

US Patent:

6344373, Feb 5, 2002

Filed:

Jun 29, 1998

Appl. No.:

09/106980

Inventors:

Arup Bhattacharyya - Essex Junction VT
Robert M. Geffken - Burlington VT
Chung H. Lam - Williston VT
Robert K. Leidy - Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2182

US Classification:

438131, 438467, 438787, 438791, 438381

Abstract:

According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.

Multi-Tier Point-To-Point Buffered Memory Interface

US Patent:

6493250, Dec 10, 2002

Filed:

Dec 28, 2000

Appl. No.:

09/753024

Inventors:

John B. Halbert - Beaverton OR
James M. Dodd - Shingle Springs CA
Chung Lam - Redwood City CA
Randy M. Bonella - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 506

US Classification:

365 63, 365 51, 365 52, 36523003

Abstract:

Methods and apparatus for a memory system using a branching point-to-point memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains a point-to-point bus connection with one memory module and that memory module maintains a separate point-to-point bus connection with a second module. Data passing between the memory controller and the second memory module passes through a buffer circuit on the first memory module. For data received from the memory controller, the buffer circuit also passes that data up a module bus segment to a first bank of memory devices. That bank of memory devices maintains a second module bus segment with a second bank of memory devices. Data passing between the buffer circuit and the second bank of memory devices passes through a pass-through circuit on the first bank of memory devices. In this manner, a point-to-point memory bus architecture can be maintained even when a memory module contains more than one bank of memory devices.

Self-Aligned Contact Areas For Sidewall Image Transfer Formed Conductors

US Patent:

6566759, May 20, 2003

Filed:

Aug 23, 1999

Appl. No.:

09/379453

Inventors:

Edward W. Conrad - Jeffersonville VT
Chung H. Lam - Williston VT
Dale W. Martin - High Park VT
Edmund Sprogis - Underhill VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257775, 257758

Abstract:

A structure for forming a sidewall image transfer conductor having a contact pad includes forming an insulator to include a recess, depositing a conductor around the insulator, and etching the conductor to form the sidewall image transfer conductor, wherein the conductor remains in the recess and forms the contact pad and the recess is perpendicular to the sidewall image transfer conductor.

Method Of Forming Merged Self-Aligned Source And Ono Capacitor For Split Gate Non-Volatile Memory

US Patent:

6352895, Mar 5, 2002

Filed:

Mar 15, 2000

Appl. No.:

09/525973

Inventors:

Chung Hon Lam - Williston VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 218247

US Classification:

438253, 438257

Abstract:

A non-volatile memory cell having a oxide-nitride-oxide (ONO) capacitor merged with a polysilicon strap diffusion region is obtained by forming a film stack on a surface of a substrate, said film stack comprising at least a floating gate oxide layer, a floating gate polysilicon later, an oxide layer and a nitride layer; forming an opening in said film stack so as to expose a portion of said floating gate polysilicon layer; forming oxide spacers in said opening; forming an oxide-nitride-oxide capacitor in said opening; forming polysilicon spacers on said oxide-nitride-oxide capacitor; providing a contact hole in said opening so as to expose a portion of said substrate; forming an oxide liner on exposed sidewalls of said contact hole; forming a source region in said substrate; forming oxide spacers from said oxide liner, wherein during the forming a portion of said substrate is re-expose; filling said opening and contact hole with doped polysilicon; and planarizing down to said nitride layer of said film stack.

Method To Create Eeprom Memory Structures Integrated With High Performance Logic And Nvram, And Operating Conditions For The Same

US Patent:

6504207, Jan 7, 2003

Filed:

Jun 30, 2000

Appl. No.:

09/609292

Inventors:

Bomy A. Chen - Ridgefield CT
Jay G. Harrington - Monroe CT
Kevin M. Houlihan - South Boston MA
Dennis Hoyniak - Essex Junction VT
Chung Hon Lam - Williston VT
Hyun Koo Lee - LaGrangeville NY
Rebecca D. Mih - Wappingers Falls NY
Jed H. Rankin - Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2976

US Classification:

257319, 257316, 257321, 438258

Abstract:

A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.

Embedded One-Time Programmable Non-Volatile Memory Using Prompt Shift Device

US Patent:

6518614, Feb 11, 2003

Filed:

Feb 19, 2002

Appl. No.:

09/683809

Inventors:

Matthew J. Breitwisch - Essex Junction VT
Bomy A. Chen - Ridgefield CT
Chung H. Lam - Williston VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27108

US Classification:

257298, 257368

Abstract:

The present invention provides a programmable element that can be programmed using relatively low-voltages (less than about 5 V) for use in one time programmable non-volatile memory storage or other high-density application. The low-voltage programmable element is a field effect transistor (FET) device that includes source and drain elements, which are separated by a channel region, and a gate region, present atop a portion of the channel region. The source and drain elements are not located beneath the gate region and the FET includes no extension implant regions present therein.

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FAQ: Learn more about Chung Lam

What is Chung Lam's current residential address?

Chung Lam's current known residential address is: 13506 Cricklewood Creek Ln, Houston, TX 77083. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Chung Lam?

Previous addresses associated with Chung Lam include: 11004 Burnside St, Portland, OR 97216; 10618 Irvin Pines Dr, Louisville, KY 40229; 1329 Huntoon Ave, Louisville, KY 40215; 11808 48Th, Kansas City, MO 64133; 18 Birch Rise Dr, Newtown, CT 06470. Remember that this information might not be complete or up-to-date.

Where does Chung Lam live?

Houston, TX is the place where Chung Lam currently lives.

How old is Chung Lam?

Chung Lam is 53 years old.

What is Chung Lam date of birth?

Chung Lam was born on 1971.

What is Chung Lam's email?

Chung Lam has such email addresses: cmoore4***@yahoo.com, paola.sa***@ibm.net, t***@bellsouth.net, julielam1***@aol.com, frl***@aol.com, cla***@mail.com. Note that the accuracy of these emails may vary and they are subject to privacy laws and restrictions.

What is Chung Lam's telephone number?

Chung Lam's known telephone numbers are: 408-251-5330, 408-996-7608, 415-397-9286, 415-681-5517, 212-619-2308, 510-895-8976. However, these numbers are subject to change and privacy restrictions.

Who is Chung Lam related to?

Known relatives of Chung Lam are: Hen Lam, Hoa Lam, Lam Lam, Stephanie Lam, Ten Lam, Catherine Lam. This information is based on available public records.

What are Chung Lam's alternative names?

Known alternative names for Chung Lam are: Hen Lam, Hoa Lam, Lam Lam, Stephanie Lam, Ten Lam, Catherine Lam. These can be aliases, maiden names, or nicknames.

What is Chung Lam's current residential address?

Chung Lam's current known residential address is: 13506 Cricklewood Creek Ln, Houston, TX 77083. Please note this is subject to privacy laws and may not be current.

Ages	43 to 79
Phones	408-251-5330	408-996-7608	415-397-9286
Addresses	30 Crescent Rd, Westport, CT 06880	11004 Burnside St, Portland, OR 97216	10618 Irvin Pines Dr, Louisville, KY 40229
Business records	Director of Technology Deployment / Isine Inc.	Senior Reliability Engineer / Varian Medical Systems	Design Lead / Ch2M Hill

Chung Lam

Information related to people with name Chung Lam

Public information about Chung Lam

Resumes

Resumes

Chung F Lam

Owner

Human Resources Manager

Retail

Technician

Expeditor, Sap

John Mcdonogh Senior High School

Principal Scientist Manager

Phones & Addresses

Business Records

Publications

Us Patents

Fabricating A Square Spacer

Nvram Array Device With Enhanced Write And Erase

Antifuse Structure And Process

Multi-Tier Point-To-Point Buffered Memory Interface

Self-Aligned Contact Areas For Sidewall Image Transfer Formed Conductors

Method Of Forming Merged Self-Aligned Source And Ono Capacitor For Split Gate Non-Volatile Memory

Method To Create Eeprom Memory Structures Integrated With High Performance Logic And Nvram, And Operating Conditions For The Same

Embedded One-Time Programmable Non-Volatile Memory Using Prompt Shift Device

FAQ: Learn more about Chung Lam

Possible Relatives

Chung Lam from other States