Chin Lim

In the United States, there are 233 individuals named Chin Lim spread across 41 states, with the largest populations residing in California, New York, Texas.

Public information about Chin Lim

Resumes

Vice President, Operations

Location:

Johnstown, PA

Industry:

Mechanical Or Industrial Engineering

Work:

Wickett & Craig of America
Vice President, Operations

Manager

Location:

1005 Blue Ravine Rd, Folsom, CA 95630

Industry:

Semiconductors

Work:

Intel since 1995
Manager

International Product Manager

Location:

Houston, TX

Industry:

Consumer Goods

Work:

Goodman Manufacturing
International Product Manager

Education:

Multimedia University
Bachelors, Engineering

Skills:

Leadership, Product Marketing, Business Strategy, Product Development, Project Management, Hvac, Hvac Controls, Product Management, Team Development

Chin Lim

Chin Joo Lim

Opc Project Management

Location:

Clifton Park, NY

Industry:

Semiconductors

Work:

Globalfoundries
Opc Project Management

Skills:

Microsoft Office, Microsoft Excel, Microsoft Word, Customer Service, Powerpoint, English, Windows, Research, Outlook, Teaching, Photoshop, Public Speaking, Html, Strategic Planning, Budgets

Languages:

German
English
Mandarin
Malay

Chin Hin Lim

Chin Ming Lim

Phones & Addresses

Name

Addresses

Phones

Chin A Lim

33854 Eastgate Cir, Corvallis, OR 97333

Chin Chong Lim

1224 Lemon St, Tempe, AZ 85281

480-966-2458

Chin Lim

Austin, TX

512-301-2625

Chin C Lim

1011 Orange St, Tempe, AZ 85281

602-966-2458, 480-966-2458

Chin C Lim

1227 Dorsey Ln, Tempe, AZ 85281

Chin Yeh Lim

Glenview, IL

847-486-0628

Chin C Lim

6932 Rosemead Blvd, San Gabriel, CA 91775

626-286-6425

Chin C Lim

8183 Crowley Cir, Buena Park, CA 90621

714-690-1503

Chin Lim

21 Surf Water Ct, Sacramento, CA 95831

916-395-4099

Chin Lim

2628 Doubletree Ln, Whittier, CA 91748

626-912-7393

Chin Lim

1033 Craig Dr, San Jose, CA 95129

Chin Lim

275 Bay 37Th St, Brooklyn, NY 11214

Chin Lim

2790 Broadway APT 5K, New York, NY 10025

212-749-0534

Chin Lim

1207 Ruby Ave, Houghton, MI 49931

Chin Lim

2913 Via Victoria, Palos Verdes Estates, CA 90274

Chin Lim

322 N Orange Ave, Monterey Park, CA 91755

Business Records

Name / Title

Company / Classification

Phones & Addresses

Chin Hu Lim
Director

KULICKE AND SOFFA INDUSTRIES, INC
Mfg Capital Equipment & Packaging Equipment · Mfg Capital Equipment and Packaging Equipment · Whol Electronic Parts/Equipment

1005 Virginia Dr, Fort Washington, PA 19034
2390 E Camelback Rd, Phoenix, AZ 85016
23A Serangoon N Ave 5 #01-01, Minneapolis, MN 55436
215-784-6000

Chin K. Lim
President

MALAYSIA SOCIETY OF SOUTHERN CALIFORNIA

123 S Figueroa St SUITE 220, Los Angeles, CA 90012

Chin Lim
Vice President Operations

Wickett & Craig of America Inc.
Leather Tanning and Finishing

120 Cooper Rd, Curwensville, PA 16833

Chin Ty Lim
President

Can Fashion, Inc

2638 Seaman Ave, El Monte, CA 91733

Chin Chian Lim
Managing

Bsbh LLC
Computer Consultant

755 E Capitol Ave, Milpitas, CA 95035

Chin Seang Lim
President

CHIN SEANG LIM, M.D., INC
Medical Doctor's Office

2012 Pray St, Fullerton, CA 92833

Chin K Lim
Manager

FRANCHISE FOR ME LLC
Nonclassifiable Establishments

6608 Magenta Ln, Austin, TX 78739

Chin Lim
VP Operations, Vice President Operations

Wickett & Craig of America Inc
Leather Tanning/Finishing · All Other Leather Good Mfg

120 Cooper Rd, Curwensville, PA 16833
814-236-2220, 814-236-3333

Publications

Us Patents

Pattern Classification Based Proximity Corrections For Reticle Fabrication

US Patent:

2016036, Dec 15, 2016

Filed:

Jun 9, 2015

Appl. No.:

14/734033

Inventors:

- Singapore, SG
Chin Teong LIM - Clifton Park NY, US
Paul ACKMANN - Gansevoort NY, US
Christian BUERGEL - Langebruck, DE

International Classification:

G03F 1/36
G06F 17/50

Abstract:

Pattern classification based proximity corrections for reticle fabrication are provided. A digital layout of a circuit design and proximity compensation data generated based on measurements of formed reticle elements are obtained. The proximity compensation data includes proximity correction values to correct for proximity effects of a reticle-formation process to form a reticle for use in fabricating a circuit of the circuit design. Based on a pattern classification of one or more patterns in the digital layout of the circuit design, at least one proximity correction is applied to the digital layout of the circuit design to facilitate correcting for proximity effects of the reticle-formation process, the at least one proximity correction being determined based on one or more of the proximity correction values of the obtained proximity compensation data. Additional adjustments to the digital layout are also provided according to aspects described herein.

Hard Mask Etch And Dielectric Etch Aware Overlap For Via And Metal Layers

US Patent:

2017006, Mar 2, 2017

Filed:

Aug 31, 2015

Appl. No.:

14/841037

Inventors:

- Grand Cayman, KY
Yuping REN - Clifton Park NY, US
David POWER - Malta NY, US
Lalit SHOKEEN - Clifton Park NY, US
Chin Teong LIM - Clifton Park NY, US
Paul W. ACKMANN - Gansevoort NY, US
Xiang HU - Clifton Park NY, US

International Classification:

G06F 17/50
G03F 1/36
G05B 15/02

Abstract:

A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.

Mask Error Compensation By Optical Modeling Calibration

US Patent:

2015031, Oct 29, 2015

Filed:

Apr 28, 2014

Appl. No.:

14/263340

Inventors:

- Grand Cayman, KY
Paul ACKMANN - Gansevoort NY, US
Chin Teong LIM - Clifton Park NY, US

International Classification:

G06F 17/50

Abstract:

Methodologies and an apparatus for enabling OPC models to account for errors in the mask are disclosed. Embodiments include: determining a patterning layer of a circuit design; estimating a penetration ratio indicating a mask corner rounding error of a fabricated mask for forming the patterning layer in a fabricated circuit; and determining, by a processor, a compensation metric for optical proximity correction of the circuit design based on the penetration ratio.

Method For Selective Re-Routing Of Selected Areas In A Target Layer And In Adjacent Interconnecting Layers Of An Ic Device

US Patent:

2017018, Jun 29, 2017

Filed:

Mar 14, 2017

Appl. No.:

15/458140

Inventors:

- Grand Cayman, KY
Yuping REN - Clifton Park NY, US
Chin Teong LIM - Clifton Park NY, US
Xusheng WU - Ballston Lake NY, US
Paul ACKMANN - Gansevoort NY, US

International Classification:

H01L 23/522
G06F 17/50
H01L 23/528
G03F 1/36

Abstract:

Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

Method Wherein Test Cells And Dummy Cells Are Included Into A Layout Of An Integrated Circuit

US Patent:

2017023, Aug 17, 2017

Filed:

May 3, 2017

Appl. No.:

15/585972

Inventors:

- Grand Cayman, KY
Paul Ackmann - Gansevoort NY, US
Guoxiang Ning - Ballston Lake NY, US
Jui-Hsuan Feng - Ballston Lake NY, US
Chin Teong Lim - Clifton Park NY, US

International Classification:

G06F 17/50

Abstract:

A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.

Achieving A Critical Dimension Target Based On Resist Characteristics

US Patent:

2016012, May 5, 2016

Filed:

Nov 5, 2014

Appl. No.:

14/533497

Inventors:

- Grand Cayman, KY
Xintuo DAI - Clifton Park NY, US
Huang LIU - Mechanicville NY, US
Chin Teong LIM - Clifton Park NY, US

International Classification:

G06F 17/50
G03F 7/34
G03F 7/32
G03F 7/16
G03F 7/20

Abstract:

Achieving a critical dimension target for a feature based on characteristics of a resist is facilitated. Mask data is established for fabricating a lithographic mask to expose different regions of a resist to high, low, and intermediate exposure levels. The resist is configured to exhibit high solubility when exposed to the high or low exposure level, and low solubility when exposed to the intermediate exposure level. A critical dimension for a region of the resist to be exposed to the intermediate exposure level is determined, and the mask data is established to indicate opaque regions for forming on the lithographic mask. The opaque regions are arrayed to facilitate exposing the region of the resist to the intermediate exposure level, to achieve the determined critical dimension. Further, a method is provided for forming in-situ a patterned mask from a mask layer above a substrate material.

Methods For Production Of Oxygenated Terpenes

US Patent:

2018013, May 17, 2018

Filed:

Aug 21, 2015

Appl. No.:

15/505503

Inventors:

- Cambridge MA, US
Chin Giaw Lim - Cambridge MA, US
Liwei Li - Cambridge MA, US
Souvik Ghosh - Cambridge MA, US
Christopher Pirie - Cambridge MA, US
Anthony Qualley - Cambridge MA, US

International Classification:

C12P 5/00
A01N 27/00
C12N 9/02
C12P 7/26

Abstract:

The present invention relates to methods for producing oxygenated terpenoids. Polynucleotides, derivative enzymes, and host cells for use in such methods are also provided.

Alternating Space Decomposition In Circuit Structure Fabrication

US Patent:

2016012, May 5, 2016

Filed:

Nov 5, 2014

Appl. No.:

14/533464

Inventors:

- Grand Cayman, KY
Xintuo DAI - Clifton Park NY, US
Huang LIU - Mechanicville NY, US
Chin Teong LIM - Clifton Park NY, US

Assignee:

GLOBALFOUNDRIES, INC. - Grand Cayman

International Classification:

G03F 7/20
G03F 7/00

Abstract:

Fabrication of a circuit structure is facilitated, in which a first exposure of a multi-layer structure is performed using a first mask, which defines positioning of at least one edge of an element to be formed above a substrate of the multi-layer structure. A second exposure of the multi-layer structure is performed using a second mask, which defines positioning of at least one other edge of the element. At least some material of the multi-layer structure is removed using, at least in part, the defined positioning of the at least one edge and the at least one other edges of the element, to form the element above the substrate. In some examples, multiple elements are formed, the multiple elements being hardmask elements to facilitate an etch process to etch a substrate material.

Videos & Images

Youtube

Jc Entertainment - Strictly Balwyn

Duration:

2m 59s

Category:

Entertainment

Description:

Elvin Ng, Nat Ho, Felicia Chin & Yvonne Lim- Lny Eve Show 2010

Duration:

1m 59s

Category:

Entertainment

Description:

Elvin Ng, Nat Ho, Felicia Chin & Yvonne Lim- LNY Eve Show 2010

Chin Lim

Duration:

5m 18s

Category:

Comedy

Description:

Chin lim

Gekisou Gt : Malaysia Drifting Report By Keiichitsuchiya With Eng Subs

Duration:

2m 55s

Category:

Autos & Vehicles

Description:

GekiSou GT : Malaysia Drifting Report by KeiichiTsuchiya with Eng Subs Hosts : Keiichi Tsuchiya and 2 famous models from Japan Drifters Leona Chin,Lim Joe Han, Wanbra, Din nismo

Nescaf Chill Lah Plex - 11 The Unexpected Love Journey

Duration:

3m 20s

Category:

Film & Animation

Description:

Www.nescafe.com.... Title The Unexpected Journey of Love. By : Tan Chin Lim. Simply by bumping into each other at a sundry shop, Wilson and Mary accidentally pick up each others phone instead of their own. And with that, a new love blooms. Also, stand a chance to win attractive prizes by casting your...

Darren Chin And Leann Lim Actual Day Wedding Video 15Th Jan 2011

Duration:

6m 4s

Category:

Travel & Events

Description:

Darren Chin and Leann Lim Actual Day Wedding Video 15th Jan 2011

Tarc Orientation Night (Penang)

Duration:

7m 30s

Category:

Howto & Style

Description:

Shuffler - Khai Ling, Chin Lim, Wei Li and Zheng Huan

Chin Lim Eat Worm

Duration:

1m 14s

Category:

Entertainment

Description:

Kelly Bay Survivor game

FAQ: Learn more about Chin Lim

What are the previous addresses of Chin Lim?

Previous addresses associated with Chin Lim include: 333 Meyer Blvd, Kansas City, MO 64113; 4920 Grand Ave, Kansas City, MO 64112; 7332 Main St, Kansas City, MO 64114; 145 Chestnut Ln, Cleveland, OH 44143; 2886 Ravine Way, Dublin, OH 43017. Remember that this information might not be complete or up-to-date.

Where does Chin Lim live?

Milpitas, CA is the place where Chin Lim currently lives.

How old is Chin Lim?

Chin Lim is 50 years old.

What is Chin Lim date of birth?

Chin Lim was born on 1974.

What is Chin Lim's email?

Chin Lim has such email addresses: lim_r***@aol.com, cyli***@yahoo.com, chin.***@yahoo.com, chin.***@bigfoot.com, chin05***@yahoo.com, jeffkay***@dellnet.com. Note that the accuracy of these emails may vary and they are subject to privacy laws and restrictions.

What is Chin Lim's telephone number?

Chin Lim's known telephone numbers are: 512-301-2625, 847-486-0628, 816-756-5526, 816-926-0840, 614-734-1797, 740-734-1797. However, these numbers are subject to change and privacy restrictions.

How is Chin Lim also known?

Chin Lim is also known as: Chinchian C Lim, H Ooi, Lim Chian, Chian L Chin, Choon C Ooi, Chian L Chinchian, H C Ooi. These names can be aliases, nicknames, or other names they have used.

Who is Chin Lim related to?

Known relatives of Chin Lim are: Elton Lim, Lu Lim, Yan Lim, Andrew Lim, Shane Saathoff, Choon Ooi, Chin Vui. This information is based on available public records.

What are Chin Lim's alternative names?

Known alternative names for Chin Lim are: Elton Lim, Lu Lim, Yan Lim, Andrew Lim, Shane Saathoff, Choon Ooi, Chin Vui. These can be aliases, maiden names, or nicknames.

What is Chin Lim's current residential address?

Chin Lim's current known residential address is: 755 Capitol, Milpitas, CA 95035. Please note this is subject to privacy laws and may not be current.

Ages	46 to 72
Phones	512-301-2625	847-486-0628	816-756-5526
Addresses	300 43Rd St, Kansas City, MO 64111	333 Meyer Blvd, Kansas City, MO 64113	4920 Grand Ave, Kansas City, MO 64112
Business records	Reseach Assistant / State University of New York at Buffalo	Senior Safety Science Leader / Genentech	Opc Project Management / Globalfoundries

Chin Lim

What do we know about Chin Lim

Public information about Chin Lim

Resumes

Resumes

Vice President, Operations

Manager

International Product Manager

Chin Lim

Chin Joo Lim

Opc Project Management

Chin Hin Lim

Chin Ming Lim

Phones & Addresses

Business Records

Publications

Us Patents

Pattern Classification Based Proximity Corrections For Reticle Fabrication

Hard Mask Etch And Dielectric Etch Aware Overlap For Via And Metal Layers

Mask Error Compensation By Optical Modeling Calibration

Method For Selective Re-Routing Of Selected Areas In A Target Layer And In Adjacent Interconnecting Layers Of An Ic Device

Method Wherein Test Cells And Dummy Cells Are Included Into A Layout Of An Integrated Circuit

Achieving A Critical Dimension Target Based On Resist Characteristics

Methods For Production Of Oxygenated Terpenes

Alternating Space Decomposition In Circuit Structure Fabrication

FAQ: Learn more about Chin Lim

Possible Relatives