FOUND IN STATES
Asim Bajwa
In the United States, there are 12 individuals named Asim Bajwa spread across 16 states, with the largest populations residing in California, New York, DC.
Last updated 2024-02-26
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Asim A Bajwa , 68
San Jose, CA
- Also known as:
- Asim Aslam Bajwa
- Asim T Bajwa
- Asima Bajwa
- Ali A Bajwa
- Has lived in:
- San Jose, CA
- Poughkeepsie, NY
- Washington, DC
- New York, NY
- Related to:
- Mahvish Zaman, 44
- Shafaq Choudry, 40
- Tauseef Choudry, 77
- Asad Choudry, 49
- Phone number:
- 408-458-****
Asim M Bajwa , 45
Glenelg, MD
- Also known as:
- Asim Bajuna
- Asim Baswa
- Asim B Revocable
- Has lived in:
- Glenelg, MD
- Columbia, MD
- Harrisburg, PA
- Ellicott City, MD
- Phone number:
- 717-805-****
- 410-312-****
Asim J Bajwa , 52
Mount Sinai, NY
- Also known as:
- Asim Bajwa
- Asim Q Bajwa
- Qasim J Bajwa
- Bajwa Qasim
- Has lived in:
- Mount Sinai, NY
- Abingdon, VA
- Gray, TN
- Bristol, VA
- Related to:
- Tarannum Bajracharya
Asim Bajwa , 36
Barstow, CA
- Also known as:
- Mahammad Bajwa
- Muhammad A Bajwa
- Bajwa Mahammad
- Has lived in:
- Barstow, CA
- Las Vegas, NV
- North Hills, CA
- Related to:
- Waqas Nazir, 47
Muhammad A Bajwa , 35
Palm Desert, CA
- Also known as:
- Ma Bajwa
- Asim M Bajwa
- Mahammad A Bajwa
- Muhammad A Bajawa
- Has lived in:
- Palm Desert, CA
- Irvine, CA
- Tustin, CA
- Las Vegas, NV
- Related to:
- Asim Bajwa
Qasim J Bajwa , 45
Abingdon, VA
- Also known as:
- Quasim J Bajwa
- Asim Q Bajwa
- Bajwa Qasim
- Has lived in:
- Abingdon, VA
- Johnson City, TN
- Midlothian, VA
- Washington, VA
- Related to:
- Padma Bajracharya, 57
Canfield, OH
- Has lived in:
- Canfield, OH
- Brunswick, OH
- Westlake, OH
- Related to:
- Taloot Bajwa
- Asim Bajwa
- Catherine Bajwa
- Eusha Bajwa, 36
North Hills, CA
- Has lived in:
- North Hills, CA
- Related to:
- Asim Bajwa, 36
- Waqas Nazir, 47
- Muhammad Baig, 27
- Nighat Baig, 64
Manchester, NH
- Has lived in:
- Manchester, NH
- Overland Park, KS
- Fort Wayne, IN
- Glendale, AZ
- Related to:
- Melinda Lightner, 52
- Melissa Helman
Public information about Asim Bajwa
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Asim Bajwa
Asim Bajwa
Asim Bajwa
Asim Bajwa
Publications
Us Patents
Non-Volatile Programmable Memory Having An Sram Capability
US Patent:
5724303, Mar 3, 1998
Filed:
Feb 15, 1996
Appl. No.:
8/601963
Inventors:
Michael E. Gannage - Santa Clara CA
David K. Wong - San Jose CA
Asim A. Bajwa - San Jose CA
David K. Wong - San Jose CA
Asim A. Bajwa - San Jose CA
Assignee:
Nexcom Technology, Inc. - Sunnyvale CA
International Classification:
G11C 700
US Classification:
3652385
Abstract:
A computer system includes a computing device such as a microcontroller and a memory device. The memory device is illustrtively a serial device connected to the serail port of the microcontrollerThe memory device includes a page latch load circuit which provides serial I/O to the microcontroller and transfers I/O bits in a predetermined order to/from the page latches. Page latches are connected over many bit lines to a memory cell array. The page latches not only supports programming and reading of sectors in the memory cell array, but also provides one or more of the following functions: directly accessable to the microcontroller as an SRAM scratch pad, directly loadable from the memory cell array to facilitate single byte "read-modify-write" operations, and loadable during programming operations to support real time applications.
Non-Volatile Programmable Memory Having A Buffering Capability And Method Of Operation Thereof
US Patent:
5862099, Jan 19, 1999
Filed:
Sep 29, 1997
Appl. No.:
8/939785
Inventors:
Michel E. Gannage - Santa Clara CA
David K. Wong - San Jose CA
Asim A. Bajwa - San Jose CA
David K. Wong - San Jose CA
Asim A. Bajwa - San Jose CA
Assignee:
Integrated Silicon Solution, Inc. - Santa Clara CA
International Classification:
G11C 700
US Classification:
3652385
Abstract:
A computer system includes a computing device such as a microcontroller and a memory device. The memory device is illustratively a serial device connected to the serial port of the microcontroller. The memory device includes a page latch load circuit which provides serial I/O to the microcontroller and transfers I/O bits in a predetermined order to/from the page latches. Page latches are connected over many bit lines to a memory cell array. The page latches not only supports programming and reading of sectors in the memory cell array, but also provides one or more of the following functions: directly accessible to the microcontroller as an SRAM scratch pad, directly loadable from the memory cell array to facilitate single byte "read-modify-write" operations, and loadable during programming operations to support real time applications.
Column Redundancy Scheme For Serially Programmable Integrated Circuits
US Patent:
6816420, Nov 9, 2004
Filed:
Jul 29, 2003
Appl. No.:
10/629109
Inventors:
Ping-Chen Liu - Fremont CA
Asim A. Bajwa - San Jose CA
Asim A. Bajwa - San Jose CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 700
US Classification:
365200, 36518902, 36518905, 36518912
Abstract:
A serially programmable integrated circuit (IC) includes a memory array and multiple data registers daisy-chained by bypass logic. Each of the data registers is associated with a primary column grouping or redundant column grouping in the memory array. If a data register is associated with a primary column grouping that includes a defective column, the bypass logic bypasses that data register and incorporates one of the data registers associated with a redundant column grouping into the serial programming path of the IC. Therefore, when a programming bitstream is shifted into this serial programming path, defective columns in the memory array are automatically bypassed during the subsequent programming operation. To read a word from the memory array, any data stored in the redundant columns is first read out, and then the data from the primary columns is read out, bypassing the previously identified defective column groupings.
Charge Pump With High Output Current
US Patent:
5216588, Jun 1, 1993
Filed:
Feb 14, 1992
Appl. No.:
7/837172
Inventors:
Asim A. Bajwa - San Jose CA
Christophe J. Chevallier - Mountain View CA
Christophe J. Chevallier - Mountain View CA
Assignee:
Catalyst Semiconductor, Inc. - Santa Clara CA
International Classification:
H02M 725
US Classification:
363 60
Abstract:
A charge pump circuit is disclosed that enables the conversion of a low voltage to a higher voltage while delivering a substantial amount of current. The charge pump circuit includes a plurality of diode-capacitor voltage multiplier pump units connected in parallel with respect to each other. The plurality of pump units are switched at different times during the pump frequency to minimize noise generation. In one embodiment, the charge pump circuit is capable of delivering 8 mA of current.
Memory Circuit With Pumped Voltage For Erase And Program Operations
US Patent:
5313429, May 17, 1994
Filed:
Feb 14, 1992
Appl. No.:
7/837303
Inventors:
Christophe J. Chevallier - Mountain View CA
Asim A. Bajwa - San Jose CA
Darrell D. Rinerson - Cupertino CA
Steve K. Hsia - Saratoga CA
Asim A. Bajwa - San Jose CA
Darrell D. Rinerson - Cupertino CA
Steve K. Hsia - Saratoga CA
Assignee:
Catalyst Semiconductor, Inc. - Santa Clara CA
International Classification:
G11C 1602
US Classification:
365226
Abstract:
A memory device is disclosed that employs hot electron injection for programming operations and Fowler-Nordheim tunneling for erase operations. The memory device requires only a single 5 volt power supply and does not require an external high voltage supply for program or erase operations. The memory device includes a charge pump section that internally generates the high voltage required for programming and erase operations. The same charge pump section is used for both program and erase power requirements.
High Voltage Regulation Circuit To Minimize Voltage Overshoot
US Patent:
6861895, Mar 1, 2005
Filed:
Jun 17, 2003
Appl. No.:
10/464129
Inventors:
Ping-Chen Liu - Fremont CA, US
Asim A. Bajwa - San Jose CA, US
Asim A. Bajwa - San Jose CA, US
International Classification:
G05F003/02
US Classification:
327536, 327565
Abstract:
A resistive divider for a voltage multiplier circuit minimizes output voltage overshoot by capacitively coupling the tap point of the resistive divider to the output terminal of the voltage multiplier circuit via the parasitic capacitance of the resistive divider. For a resistive divider that includes a resistive structure formed over a dielectric layer formed on a doped well, this capacitive coupling can be performed by connecting the well to the output terminal of the voltage multiplier circuit. This capacitive coupling improves the response time of the resistive divider, so that a scaled test voltage read from the tap point varies more rapidly than the elevated output voltage of the voltage multiplier circuit. Therefore, the scaled test voltage provides charging control that increases the elevated output voltage in gradual increments that prevent the elevated output voltage from exceeding a target output voltage.
Column Redundancy Scheme For Non-Volatile Flash Memory Using Jtag Input Protocol
US Patent:
7088627, Aug 8, 2006
Filed:
Jul 29, 2003
Appl. No.:
10/629365
Inventors:
Asim A. Bajwa - San Jose CA, US
Ping-Chen Liu - Fremont CA, US
Ping-Chen Liu - Fremont CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 7/00
US Classification:
365200, 365201, 36518902, 36518912, 36518905
Abstract:
A JTAG-programmable IC includes a memory array having redundant columns, a partial-width data register, and a full-width bitline register. A programming bitstream is shifted into the data register in discrete portions, with each portion being loaded into the bitline latch before the next portion is shifted into the data register. The programming bitstream portions fill the bitline latch sequentially unless a count indicator for a particular portion matches a predetermined defective column value, in which case that bitstream portion is rerouted to a region of the bitline latch associated with the redundant columns of the memory array. The count indicator is incremented with each new bitstream portion shifted into the data register. Once the programming bitstream is fully loaded into the bitline latch, the data is programmed into a selected row of the memory array in page mode.
Program Latch With Charge Sharing Immunity
US Patent:
6262920, Jul 17, 2001
Filed:
Aug 25, 1999
Appl. No.:
9/382347
Inventors:
Benjamin Louie - Sunnyvale CA
Asim Bajwa - San Jose CA
Asim Bajwa - San Jose CA
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 1604
US Classification:
36518905
Abstract:
A method and apparatus for loading portions of a bank of program latches in parallel while providing charge sharing immunity is described. A latch is bypassed while it is loaded, thereby coupling the input to the output, so that any capacitance on the output is charged. In later load operations, when the input to the latch is not driven with data, but is rather left to float, the output is again coupled to the input so that the charged capacitance on the output keeps the input from changing state. The program latches can be used as part of a memory device, to hold data on shared bitlines in columns of a memory array while the array is programmed. The program latches are controlled by a latch load signal and a latch bypass signal, both of which are fanned out across the bank of program latches.
FAQ: Learn more about Asim Bajwa
What is Asim Bajwa's telephone number?
Asim Bajwa's known telephone numbers are: 410-312-4820, 717-805-3165, 408-458-0569, 408-398-7158, 276-676-2475, 410-418-8317. However, these numbers are subject to change and privacy restrictions.
How is Asim Bajwa also known?
Asim Bajwa is also known as: Asim Aslam Bajwa, Asim T Bajwa, Asima Bajwa, Ali A Bajwa, Asim Aslam, Aslam B Atiq. These names can be aliases, nicknames, or other names they have used.
Who is Asim Bajwa related to?
Known relatives of Asim Bajwa are: Mahvish Zaman, Shafaq Choudry, Tauseef Choudry, Asad Choudry, Javid Maaria. This information is based on available public records.
What are Asim Bajwa's alternative names?
Known alternative names for Asim Bajwa are: Mahvish Zaman, Shafaq Choudry, Tauseef Choudry, Asad Choudry, Javid Maaria. These can be aliases, maiden names, or nicknames.
What is Asim Bajwa's current residential address?
Asim Bajwa's current known residential address is: 4955 Fontanelle Pl, San Jose, CA 95111. Please note this is subject to privacy laws and may not be current.
What are the previous addresses of Asim Bajwa?
Previous addresses associated with Asim Bajwa include: 14103 Patterson Farm Ct, Glenelg, MD 21737; 2 Hunters Ridge Rd, Johnson City, TN 37604; 4100 Sw Edmunds St Apt 222, Seattle, WA 98116; 4903 Bridgeview, San Jose, CA 95138; 4955 Fontanelle Pl, San Jose, CA 95111. Remember that this information might not be complete or up-to-date.
Where does Asim Bajwa live?
San Jose, CA is the place where Asim Bajwa currently lives.
How old is Asim Bajwa?
Asim Bajwa is 68 years old.
What is Asim Bajwa date of birth?
Asim Bajwa was born on 1956.
What is Asim Bajwa's email?
Asim Bajwa has email address: aba***@peoplepc.com. Note that the accuracy of this email may vary and this is subject to privacy laws and restrictions.