Arthur Leung

In the United States, there are 38 individuals named Arthur Leung spread across 17 states, with the largest populations residing in California, Massachusetts, Arizona.

Public information about Arthur Leung

Resumes

Arthur Leung

Location:

United States

Arthur Leung

Location:

San Francisco Bay Area

Industry:

Accounting

Cofounder + Designer + Front End Developer At Digmybrand

Position:

Cofounder + designer + front end developer at digmybrand

Location:

Greater Los Angeles Area

Industry:

Design

Work:

Digmybrand - Greater Los Angeles Area since Feb 2013
cofounder + designer + front end developer RED Interactive Agency - Santa Monica Jun 2012 - Feb 2013
User Experience Designer philosophie LLC - Greater Los Angeles Area Jan 2012 - May 2012
User Interface Designer / Info Architect Johnson & Johnson - Greater Los Angeles Area Sep 2010 - Jan 2012
Design Strategist Art Center College of Design May 2008 - Jul 2008
Design Intern - Art Center Pro Studio and Disney Consumer Products MAN Diesel - Copenhagen Area, Denmark Aug 2004 - May 2006
Mechanical Engineer

Education:

Art Center College of Design 2007 - 2010
BS, Product Design INSEAD 2009 - 2009
MBA, Entrepreneur California Institute of Technology 2008 - 2008
The University of British Columbia 2000 - 2004
BASc, Mechanical Engineering

Skills:

Research Design, User Interface Design, Brand Development, Presentation Development, Product Strategy, Workshop Design, Digital Strategy, Digital Design, Design Strategy, Product Design, User-centered Design, User Experience

Interests:

Travel, Design, Food,

Honor & Awards:

Gold Prize Winner, Shanghai International Student Biennale

Languages:

English
Chinese
Danish

Arthur Leung - Saratoga, CA

Work:

Juniper Networks 2012 to 2000
Architect and Lead Design Engineer for Fabric Packet Reassembly Huawei Technologies - Santa Clara, CA 2008 to 2012
Architect for scalable 120G Core and Service Cisco Systems - San Jose, CA 2004 to 2008 Procket Networks - Milpitas, CA 1999 to 2004
Architect and Lead Designer, Network Processor Chip Sun Microsystems - Mountain View, CA 1994 to 1999
Project Leader, Integer Execution Unit Sun Microsystems - Mountain View, CA 1992 to 1994
Lead Design Engineer, Integer Unit Sun Microsystems - Mountain View, CA 1990 to 1992
Lead Design Engineer, Integer Unit Sun Microsystems - Mountain View, CA 1988 to 1990
Design Engineer, Integer Unit, SUNTAN ECL SPARC CPU Sun Microsystems - Mountain View, CA 1987 to 1988
Intern, Verification Engineer, Integer and Floating Point Units

Education:

Stanford University - Stanford, CA 1988
MSEE Stanford University - Stanford, CA 1987
BSEE in engineering

Arthur Leung - Oakland, CA

Work:

SFSU EMT Department - San Francisco, CA Mar 2014 to Dec 2015
Student Assistant Fuddruckers - Emeryville, CA Jul 2012 to Jul 2013
Cashier

Education:

San Francisco State University - San Francisco, CA 2010 to 2014
Bachelor of Science in Business Administration - Management

Skills:

Fluent in English and Cantonese, Quick Learner, Adaptable, Powerful work ethic, Strong communication skills,

Arthur Leung

Position:

O at O

Location:

Rowland Heights, California

Industry:

Arts and Crafts

Work:

O since May 2011
O

Arthur Leung - Emeryville, CA

Work:

San Francisco County Transportation Authority Oct 2010 to 2000
Transportation Planning Intern Safe Transportation Research and Education Center (SafeTREC) - Berkeley, CA Aug 2009 to May 2010
Graduate Student Researcher Protective Structure Sections - San Antonio, TX Jan 2008 to Aug 2008
Co-Op Student Intern Center of Transportation Research, UT Austin - Austin, TX May 2007 to Aug 2007
Undergraduate Research Assistant

Education:

University of California, Berkeley - Berkeley, CA Jan 2009 to Jan 2010
Master of Science in Transportation Engineering/Planning The University of Texas at Austin - Austin, TX Jan 2005 to Jan 2009
Bachelor of Science in Civil Engineering

Skills:

ArcGIS, AutoCAD, C++, cube, GEOPAK, Office, Microstation, SYNCRO, SPSS, VBA

Principal Software Engineer At Medplus

Position:

Principal Software Engineer at MedPlus

Location:

Cincinnati Area

Industry:

Computer Software

Work:

MedPlus
Principal Software Engineer

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Phones & Addresses

Name

Addresses

Phones

Arthur Leung

1555 Union St, Sparks, NV 89434

775-359-5087

Arthur P Leung

1775 Egret Ln, Hayward, CA 94545

510-782-6975

Arthur Leung

15728 26Th Ave, Flushing, NY 11354

718-746-3991

Arthur S Leung

6024 Hart Ave, Temple City, CA 91780

626-451-0946

Arthur S Leung

6925 Rosemead Blvd, San Gabriel, CA 91775

626-309-0176

Arthur Y Leung

846 41St Ave, San Francisco, CA 94121

310-561-5591

Arthur S Leung

4850 Cool Springs Dr, Reno, NV 89509

775-826-1836

Arthur T Leung

11136 Whispering Heights Ln, San Diego, CA 92121

858-638-7232

Business Records

Name / Title

Company / Classification

Phones & Addresses

Arthur Leung
Family And General Dentistry

Arthur Leung DDS
Dentist's Office · Dentists

3575 Grant Dr, Reno, NV 89509
775-825-4070

Arthur Leung
Secretary

Citilabs
Transportation/Trucking/Railroad

1211 Miccosukee Rd, Tallahassee, FL 32308
842 41 Ave, San Francisco, CA 94121

Arthur Leung
CTO

America West Airlines
Air Transportation, Scheduled

1920 W University Dr, Tempe, AZ 85281

Arthur Leung
Director of Operations

Accenture Inc
Management Consulting Services · Nonclassifiable Establishments

180 N Ln Salle St, Chicago, IL 60601

Arthur Leung

Bonforte and Leung Investments, LLC
Investor

5758 Geary Blvd, San Francisco, CA 94121
842 41 Ave, San Francisco, CA 94121

Arthur Leung
Vice President

Arthur Leung
Legislative Bodies

1775 Egret Ct, Hayward, CA 94544

Arthur Yin Wah Leung

EAGLE PINE PROPERTIES, LLC

612 S Copeland St, Tallahassee, FL 32304

Arthur Leung
President

PALO ALTO KENDO DOJO

2568 Yerba Bank Ct, San Jose, CA 95121
38080 Martha Ave, Fremont, CA 94536

Publications

Us Patents

Execution Unit And Method For Executing Performance Critical And Non-Performance Critical Arithmetic Instructions In Separate Pipelines

US Patent:

5948098, Sep 7, 1999

Filed:

Jun 30, 1997

Appl. No.:

8/885622

Inventors:

Arthur T. Leung - Sunnyvale CA
Gary R. Lauterbach - Los Altos CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 900

US Classification:

712221

Abstract:

A CPU (central processing unit) of a computer that comprises an issue unit and an execution unit. The issue unit selectively issues arithmetic instructions of a predefined arithmetic instruction type as performance critical arithmetic instructions and non-performance critical arithmetic instructions. The execution unit comprises a performance critical pipeline to execute the performance critical arithmetic instructions. The execution unit also comprises a non-performance critical pipeline to execute the non-performance critical arithmetic instructions.

Window Delta From Current Window For Fast Register File Address Dependency Checking

US Patent:

5799166, Aug 25, 1998

Filed:

Jun 17, 1996

Appl. No.:

8/664479

Inventors:

Arthur T. Leung - Sunnyvale CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 934

US Classification:

395392

Abstract:

A simplified comparison of register designations by using a window delta which indicates how much the window of an instruction differs from the current window register designation. Where registers are shared, the windows will either be the same or differ by one. Thus, a single bit can be used to indicate the window delta, and in combination with the logical register address, can be used to quickly determine whether there is a register match between instructions.

Processor Having Systolic Array Pipeline For Processing Data Packets

US Patent:

7418536, Aug 26, 2008

Filed:

Jan 4, 2006

Appl. No.:

11/326253

Inventors:

Arthur Tung-Tak Leung - Saratoga CA, US
Anthony Li - Los Altos CA, US
William Lynch - La Honda CA, US
Sharad Mehrotra - Saratoga CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 13/36

US Classification:

710306, 710 38, 712 10, 712 11, 712 19, 709238

Abstract:

A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of programmable functional units and register files arranged sequentially as stages, for processing packet contexts (which contain the packet's destination address) to perform operations, under programmatic control, to determine the destination port of the router for the packet. A single stage of the systolic array may contain a register file and one or more functional units such as adders, shifters, logical units, etc. , for performing, in one example, very long instruction word (vliw) operations. The processor may also include a forwarding table memory, on-chip, for storing routing information, and a cross bar selectively connecting the stages of the systolic array with the forwarding table memory.

Execution Unit And Method For Using Architectural And Working Register Files To Reduce Operand Bypasses

US Patent:

5964862, Oct 12, 1999

Filed:

Jun 30, 1997

Appl. No.:

8/884699

Inventors:

Arthur T. Leung - Sunnyvale CA
Gary R. Lauterbach - Los Altos CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 938

US Classification:

712 23

Abstract:

A CPU (central processing unit) of a computer. The CPU comprises a dispatch controller, a pipeline, a working register file, and an architectural register file. The dispatch controller dispatches instructions for execution and determines whether the dispatched instructions are valid or invalid. The pipeline executes the dispatched instructions using selected operands in the pipeline and generates operands in response. The working register file stores the generated operands before the executed instructions are determined to be valid or invalid by the dispatch controller such that the stored operands may be subsequently selected for use in executing an instruction in the pipeline. The architectural register file stores the generated operands for those of the executed instructions that are determined to be valid by the dispatch controller and transfer operands currently stored therein when one of the executed instructions is determined to be invalid by the dispatch logic. The working register file then stores the transferred operands such that the transferred operands may be subsequently selected for use in executing an instruction in the pipeline.

Burn-In System For Reliable Integrated Circuit Manufacturing

US Patent:

5798653, Aug 25, 1998

Filed:

Apr 20, 1995

Appl. No.:

8/425975

Inventors:

Arthur T. Leung - Sunnyvale CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G01R 3500
G01R 3102

US Classification:

324760

Abstract:

A burn-in system for integrated circuits (ICs) generates thorough input stimuli from within the burn-in chamber. A very high node-toggle percentage within the IC being exercised is achieved, similar to that of a dynamic burn-in oven, even though the burn-in system of this invention has a cost and complexity similar to that of a static burn-in oven. This provides a cost-effective and reliable way to reduce the infant mortality of the ICs being exercised, or to estimate the longevity of the batch of ICs from which they came. The input-stimuli generator is based on a special-purpose burn-in controller IC. To better withstand the environmental stress within the burn-in chamber, the burn-in controller IC is fabricated using a robust IC technology, is operated at its nominal supply voltage and includes continuous fault tolerance features (such as self-test and/or voting). It is fully programmable to allow the same burn-in controller to be used with a variety of types of ICs being exercised. In accordance with another aspect of this invention, the input-stimuli generator loads instruction memory internal to the ICs being exercised with a self-exercise program and then waits while they execute this self-exercise program.

Fast Handling Of Branch Delay Slots On Mispredicted Branches

US Patent:

5784603, Jul 21, 1998

Filed:

Jun 19, 1996

Appl. No.:

8/665964

Inventors:

Arthur Leung - Sunnyvale CA
Joseph Petolino - Palo Alto CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 938

US Classification:

395581

Abstract:

An apparatus and method for quickly and efficiently handling mispredicted branch instructions in a computer processor having multiple instruction execution pipelines and utilizing branch delay slot instructions. When a mispredicted branch occurs, all instructions that follow the branch in execution order, including the branch delay slot instruction, die in the pipeline. The delay slot, if it is to be executed, is then reissued to the pipeline.

Methods And Apparatus For Synchronizing Asynchronous Test Structures And Eliminating Clock Skew Considerations

US Patent:

6185711, Feb 6, 2001

Filed:

Dec 3, 1998

Appl. No.:

9/204557

Inventors:

Arthur T. Leung - Sunnyvale CA
Dale Greenley - Los Gatos CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 1100

US Classification:

714731

Abstract:

A synchronizing circuit receives an external signal and yields an output that is synchronized with the system clock and operates at the frequency of the external signal. The signal output from the synchronizing circuit is fed into the clock-enable input of the storage element, and the system clock signal is fed into the clock input of the storage element. Because the clock-enable signal triggers the storage element, the storage element is driven at the external signal frequency. Clock skew is eliminated because the system clock used for the clock input to the storage element is skew-controlled.

Method For Dependency Checking Using A Scoreboard For A Pair Of Register Sets Having Different Precisions

US Patent:

5790827, Aug 4, 1998

Filed:

Jun 20, 1997

Appl. No.:

8/879589

Inventors:

Arthur T. Leung - Sunnyvale CA

Assignee:

Sun Microsystems, Inc. - Sunnyvale CA

International Classification:

G06F 938
G06F 922

US Classification:

395392

Abstract:

A dependency checking method includes a scoreboard which records destination operands of instructions outstanding within the pipeline of a microprocessor. Each single precision register maps to an indication within the scoreboard. Each double precision register which does not overlap with single precision registers maps to an indication within the scoreboard. Double precision registers which overlap single precision registers map to the set of indications corresponding to the overlapping single precision registers. Dependency checking for a source operand is performed by forming a first set of indications corresponding to the double precision registers and a second set of indications corresponding to the single precision registers, then selecting a dependency indication from these sets of indications in response to the source precision and the source register address. By forming the first and second sets of indications, the source register address can be used directly to select the dependency indication from each of the first and second sets of indications.

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FAQ: Learn more about Arthur Leung

What is Arthur Leung's telephone number?

Arthur Leung's known telephone numbers are: 718-746-3991, 310-561-5591, 510-862-0331, 281-785-8378, 480-246-4670, 408-446-1935. However, these numbers are subject to change and privacy restrictions.

How is Arthur Leung also known?

Arthur Leung is also known as: Art Leung, Athur H Leung. These names can be aliases, nicknames, or other names they have used.

Who is Arthur Leung related to?

Known relatives of Arthur Leung are: Grant Leung, Susan Leung, Valerie Leung, Rose Humbert, Myles Megyesi, Curtis Megyesi. This information is based on available public records.

What are Arthur Leung's alternative names?

Known alternative names for Arthur Leung are: Grant Leung, Susan Leung, Valerie Leung, Rose Humbert, Myles Megyesi, Curtis Megyesi. These can be aliases, maiden names, or nicknames.

What is Arthur Leung's current residential address?

Arthur Leung's current known residential address is: 3604 Glengary Ln, Cincinnati, OH 45236. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Arthur Leung?

Previous addresses associated with Arthur Leung include: 846 41St Ave, San Francisco, CA 94121; 1775 Egret Ct, Hayward, CA 94545; 5817 155Th St, Flushing, NY 11355; 12009 Sundance Ct, Stafford, TX 77477; 14208 Silent Wood Way, Gaithersburg, MD 20878. Remember that this information might not be complete or up-to-date.

Where does Arthur Leung live?

Cincinnati, OH is the place where Arthur Leung currently lives.

How old is Arthur Leung?

Arthur Leung is 63 years old.

What is Arthur Leung date of birth?

Arthur Leung was born on 1961.

What is Arthur Leung's email?

Arthur Leung has such email addresses: wendyale***@aol.com, arthur.le***@msn.com, crzyswtan***@comcast.net, arthurle***@hotmail.com, arthurkle***@address.com, shiniga***@hotmail.com. Note that the accuracy of these emails may vary and they are subject to privacy laws and restrictions.

Name Variants	Art Leung	Artie Leung	Arty Leung
Ages	35 to 84
Phones	718-746-3991	310-561-5591	510-862-0331
Addresses	15728 26Th Ave, Flushing, NY 11354	846 41St Ave, San Francisco, CA 94121	1775 Egret Ct, Hayward, CA 94545
Business records	Cofounder + designer + front end developer / Digmybrand	Senior Staff Engineer / Juniper Networks	Consultant / Booz Allen Hamilton

Arthur Leung

What do we know about Arthur Leung

Public information about Arthur Leung

Resumes

Resumes

Arthur Leung

Arthur Leung

Cofounder + Designer + Front End Developer At Digmybrand

Arthur Leung - Saratoga, CA

Arthur Leung - Oakland, CA

Arthur Leung

Arthur Leung - Emeryville, CA

Principal Software Engineer At Medplus

Phones & Addresses

Business Records

Publications

Us Patents

Execution Unit And Method For Executing Performance Critical And Non-Performance Critical Arithmetic Instructions In Separate Pipelines

Window Delta From Current Window For Fast Register File Address Dependency Checking

Processor Having Systolic Array Pipeline For Processing Data Packets

Execution Unit And Method For Using Architectural And Working Register Files To Reduce Operand Bypasses

Burn-In System For Reliable Integrated Circuit Manufacturing

Fast Handling Of Branch Delay Slots On Mispredicted Branches

Methods And Apparatus For Synchronizing Asynchronous Test Structures And Eliminating Clock Skew Considerations

Method For Dependency Checking Using A Scoreboard For A Pair Of Register Sets Having Different Precisions

FAQ: Learn more about Arthur Leung

Possible Relatives