Alvin Ching

22 individuals named Alvin Ching found in 13 states. Most people reside in California, Hawaii, Arizona.

Public information about Alvin Ching

Resumes

Student At Western Career College

Location:

San Francisco Bay Area

Industry:

Medical Practice

Alvin Ching

Ic Design Manager

Location:

Sunnyvale, CA

Industry:

Semiconductors

Work:

Xilinx
Ic Design Manager

Education:

University of California, Los Angeles
Master of Science, Masters, Bachelors, Bachelor of Science, Electrical Engineering

Skills:

Integrated Circuit Design, Soc, Fpga, Semiconductors, Ic

Alvin Ching

Industry:

Consumer Services

Work:

Pc Florist 2010 - 2012
Driver

Retired

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Data provided by Veripages

Phones & Addresses

Name

Addresses

Phones

Alvin L Ching

1118 Cassidy St, Gardena, CA 90248

310-324-6880

Alvin L Ching

140 Fairmont Blvd, Anaheim, CA 92808

714-637-3240

Alvin Woodard W Ching

404 Vintage Hill Dr, Greenville, SC 29609

864-349-1445

Alvin S Ching

4521 Shed Rd, Bossier City, LA 71111

Alvin W Ching

26 Hillandale Cir, Greenville, SC 29609

864-255-9521

Alvin Ching

403 Main St, El Segundo, CA 90245

Alvin W Ching

26 Hillandale Rd, Greenville, SC 29609

864-255-9521

Alvin W Ching

524 Sudden Vly, Bellingham, WA 98225

360-647-7678

Publications

Us Patents

Mathematical Circuit With Dynamic Rounding

US Patent:

7467177, Dec 16, 2008

Filed:

Dec 21, 2004

Appl. No.:

11/019853

Inventors:

James M. Simkins - Park City UT, US
Steven P. Young - Boulder CO, US
Jennifer Wong - Fremont CA, US
Bernard J. New - Carmel Valley CA, US
Alvin Y. Ching - Sunnyvale CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 7/38

US Classification:

708551

Abstract:

Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2and 2−1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.

Programmable Logic Device With Cascading Dsp Slices

US Patent:

7472155, Dec 30, 2008

Filed:

Dec 21, 2004

Appl. No.:

11/019783

Inventors:

James M. Simkins - Park City UT, US
Steven P. Young - Boulder CO, US
Jennifer Wong - Fremont CA, US
Bernard J. New - Carmel Valley CA, US
Alvin Y. Ching - Sunnyvale CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 7/38

US Classification:

708523

Abstract:

Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.

Digital Phase Shifter

US Patent:

6775342, Aug 10, 2004

Filed:

Oct 6, 2000

Appl. No.:

09/684540

Inventors:

Steven P. Young - Boulder CO
John D. Logue - Placerville CA
Andrew K. Percey - San Jose CA
F. Erich Goetting - Cupertino CA
Alvin Y. Ching - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04L 2500

US Classification:

375371, 375373, 375376, 327158, 327161

Abstract:

After a delay lock loop synchronizes a reference clock signal with a skewed clock signal, a digital phase shifter can be used to shift the skewed clock signal by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay, which is referenced to the period of the reference clock signal, to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal. The digital phase shifter can be controlled to operate in several modes. In a first fixed mode, the digital phase shifter introduces delay to the skew clock signal.

Arithmetic Circuit With Multiplexed Addend Inputs

US Patent:

7480690, Jan 20, 2009

Filed:

Dec 21, 2004

Appl. No.:

11/019854

Inventors:

James M. Simkins - Park City UT, US
Steven P. Young - Boulder CO, US
Jennifer Wong - Fremont CA, US
Bernard J. New - Carmel Valley CA, US
Alvin Y. Ching - Sunnyvale CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G06F 7/48

US Classification:

708523, 708501

Abstract:

Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.

Automatic Tap Delay Calibration For Precise Digital Phase Shift

US Patent:

7564283, Jul 21, 2009

Filed:

Apr 30, 2004

Appl. No.:

10/837059

Inventors:

John D. Logue - Placerville CA, US
Alvin Y. Ching - San Jose CA, US
Wei Guang Lu - San Jose CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H03L 7/06
H03H 11/16

US Classification:

327234, 327158

Abstract:

An automatic calibration scheme is provided, which calibrates the equivalent taps per period ETT/P every time a delay lock loop is used. More specifically, a digital phase shifter is used to measure equivalent taps per period ETT/P. Alternately, the digital phase shifter is used to directly measure the signal delay through a clock phase shifter of the delay lock loop, thereby directly determining the high frequency and low frequency overhead constants.

Memory Device And Method Of Transferring Data In Memory Device

US Patent:

7242633, Jul 10, 2007

Filed:

Jan 26, 2005

Appl. No.:

11/044740

Inventors:

Alvin Y. Ching - Sunnyvale CA, US
Raymond C. Pang - San Jose CA, US
Steven P. Young - Boulder CO, US
Thanh Pham - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G11C 8/00

US Classification:

36523005, 36518904

Abstract:

According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.

Applications Of Cascading Dsp Slices

US Patent:

7567997, Jul 28, 2009

Filed:

Dec 21, 2004

Appl. No.:

11/019518

Inventors:

James M. Simkins - Park City UT, US
Steven P. Young - Boulder CO, US
Jennifer Wong - Fremont CA, US
Bernard J. New - Carmel Valley CA, US
Alvin Y. Ching - Sunnyvale CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G06F 7/48

US Classification:

708523

Abstract:

In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.

Digital Signal Processing Circuit Having Input Register Blocks

US Patent:

7840627, Nov 23, 2010

Filed:

May 12, 2006

Appl. No.:

11/432823

Inventors:

James M. Simkins - Park City UT, US
Jennifer Wong - Fremont CA, US
Bernard J. New - Carmel Valley CA, US
Alvin Y. Ching - Sunnyvale CA, US
John M. Thendean - Berkeley CA, US
Anna Wing Wah Wong - Santa Clara CA, US
Vasisht Mantra Vadi - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 7/38

US Classification:

708490

Abstract:

An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.

Videos & Images

Youtube

Jenny James At Heal The World By Filipino Canadian Artists

Duration:

6m 1s

Category:

Music

Description:

A charity event for the typhoon victims in the Philippines (Jenny +James) Jenny James Venue: Gateway Centre Mississauga Ontario Date: Oct 17,2009 Music Arranger: Rodney Ronquillo Producer: Rei Ching Performers: Josie de Leon, Jenny James, Emilio Zarris, Alvin Alba, Todd Domingo, Rommel Billanes, Ric...

3m 24s

Category:

Music

Alvin & Die Chipmunks-Ching Ching

Duration:

4m 19s

Category:

Music

FAQ: Learn more about Alvin Ching

What is Alvin Ching's current residential address?

Alvin Ching's current known residential address is: 404 Vintage Hill Dr, Greenville, SC 29609. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Alvin Ching?

Previous addresses associated with Alvin Ching include: 4021 Garvey Way, Riverside, CA 92501; 98-1769 Hapaki St, Aiea, HI 96701; 403 Main St, El Segundo, CA 90245; 13247 Foothill Blvd Apt 13206, Rch Cucamonga, CA 91739; 2870 Highview Ter # 115, Saint Paul, MN 55121. Remember that this information might not be complete or up-to-date.

Where does Alvin Ching live?

Sunnyvale, CA is the place where Alvin Ching currently lives.

How old is Alvin Ching?

Alvin Ching is 51 years old.

What is Alvin Ching date of birth?

Alvin Ching was born on 1972.

What is Alvin Ching's telephone number?

Alvin Ching's known telephone numbers are: 864-349-1445, 619-360-1529, 808-486-5538, 626-297-3757, 952-686-5802, 408-559-0110. However, these numbers are subject to change and privacy restrictions.

How is Alvin Ching also known?

Alvin Ching is also known as: Alvin G Ching, Alviny Ching, Alvin Chiang. These names can be aliases, nicknames, or other names they have used.

Who is Alvin Ching related to?

Known relatives of Alvin Ching are: Inna Morris, Steven Chin, Jodie Ching, Sonia Ching, Alden Ching, Alson Ching, Alvin Ching, Cathy Tsuchihashi, Jake Syga, Jonathan Syga, Ma Syga. This information is based on available public records.

What are Alvin Ching's alternative names?

Known alternative names for Alvin Ching are: Inna Morris, Steven Chin, Jodie Ching, Sonia Ching, Alden Ching, Alson Ching, Alvin Ching, Cathy Tsuchihashi, Jake Syga, Jonathan Syga, Ma Syga. These can be aliases, maiden names, or nicknames.

What is Alvin Ching's current residential address?

Alvin Ching's current known residential address is: 404 Vintage Hill Dr, Greenville, SC 29609. Please note this is subject to privacy laws and may not be current.

Name Variants	Alwin Ching	Alwyn Ching	Al Ching
Ages	38 to 87
Phones	864-349-1445	619-360-1529	808-486-5538
Addresses	404 Vintage Hill Dr, Greenville, SC 29609	4021 Garvey Way, Riverside, CA 92501	98-1769 Hapaki St, Aiea, HI 96701
Business records	Ic Design Manager / Xilinx	Driver / Pc Florist

Alvin Ching

Information related to people with name Alvin Ching

Public information about Alvin Ching

Resumes

Resumes

Student At Western Career College

Alvin Ching

Ic Design Manager

Alvin Ching

Retired

Phones & Addresses

Publications

Us Patents

Mathematical Circuit With Dynamic Rounding

Programmable Logic Device With Cascading Dsp Slices

Digital Phase Shifter

Arithmetic Circuit With Multiplexed Addend Inputs

Automatic Tap Delay Calibration For Precise Digital Phase Shift

Memory Device And Method Of Transferring Data In Memory Device

Applications Of Cascading Dsp Slices

Digital Signal Processing Circuit Having Input Register Blocks

FAQ: Learn more about Alvin Ching

Possible Relatives