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Akash Bansal

In the United States, there are 8 individuals named Akash Bansal spread across 10 states, with the largest populations residing in Texas, Pennsylvania, California. These Akash Bansal range in age from 26 to 52 years old. Some potential relatives include Ashish Bansal, Meera Bansal, Anirudh Bansal. You can reach Akash Bansal through their email address, which is aban***@alltel.net. The associated phone number is 412-908-0835, along with 6 other potential numbers in the area codes corresponding to 510, 408, 404. For a comprehensive view, you can access contact details, phone numbers, addresses, emails, social media profiles, arrest records, photos, videos, public records, business records, resumes, CVs, work history, and related names to ensure you have all the information you need.
Last updated Mar 10, 2024
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Akash Bansal , Age 52
Santa Clara, CA
Also known as:
I Bansal
Bansal Akash
Has lived in:
Santa Clara, CA
Sunnyvale, CA
Fremont, CA
Los Angeles, CA
Related to:
Vikas Bansal, 45
Kailash Jayaswal, 57
Archana Jayaswal, 55
Arpana Jayaswal, 49
Phone number:
408-529-****
510-687-****
PhoneAddress
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Akash Bansal , Age 26
Wexford, PA
Has lived in:
Wexford, PA
Related to:
Sejal Shah, 51
Ashok Gupta, 67
Dipti Sheth, 57
Hiren Sheth, 69
Phone number:
412-908-****
PhoneAddress
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Akash Bansal , Age 47
Sugar Land, TX
Has lived in:
Sugar Land, TX
Houston, TX
Atlanta, GA
Related to:
Meera Bansal
Priyanka Bansal, 43
Anirudh Bansal
Ashish Bansal
Phone number:
404-963-****
PhoneAddress
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Akash Bansal , Age 48
Germantown, TN
Has lived in:
Germantown, TN
San Antonio, TX
Frederick, MD
Houston, TX
Phone number:
210-641-****
301-682-****
PhoneAddress
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Akash Bansal , Age 36
Austin, TX
Has lived in:
Austin, TX
Durham, NC
Dallas, TX
Paris, VA
Related to:
Umesh Bansal
PhoneAddress
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Akash Bansal 
Paoli, PA
Has lived in:
Paoli, PA
Sacramento, CA
Rancho Cordova, CA
West Chester, PA
PhoneAddress
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Akash Bansal 
Austin, TX
Has lived in:
Austin, TX
Dallas, TX
Related to:
Umesh Bansal
PhoneAddress
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Akash Bansal 
Philadelphia, PA
Has lived in:
Philadelphia, PA
PhoneAddress
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Public information about Akash Bansal

Resumes

Resumes

Akash Bansal

Akash Bansal Photo 1
Location:
Pittsburgh, PA
Education:
Carnegie Mellon University's College of Engineering 2016 - 2020

Us It Recruiter

Akash Bansal Photo 2
Location:
Atlanta, GA
Work:
Nityo Infotech
Us It Recruiter

Akash Bansal

Akash Bansal Photo 3
Location:
2025 Gateway Pl, San Jose, CA 95110
Industry:
Information Technology And Services
Work:
California Department of Justice Jul 2015 - Apr 2019
Java Consultant at California Department of Justice Cognizant Technology Solutions Nov 2014 - Jul 2015
Technical Architect Synechron May 2014 - Nov 2014
Technical Lead Dell Jul 2010 - May 2014
Senior Analyst - Software Development Ncr Corporation Mar 2010 - Jun 2010
Software Engineer Inventive Software Solutions Pvt.ltd Oct 2007 - Feb 2010
Senior Software Developer
Skills:
Java Enterprise Edition, Hibernate, Java, Ejb, Xml, Spring, Spring Framework, Design Patterns, Jsp, Servlets, Struts, Software Development, Agile Methodologies, Oracle, Sql, Core Java, Soap, Jee 5/6, Javase, Maven, Jboss Eap, Restful Webservices, Soap Web Services, Edi Ansi X12, Drools, Activiti Workflow, Service Oriented Architecture Design, Jboss Seam, Jsf, Mule Esb, Angularjs, Jquery, Apache Camel, Spring Integration, Spring Batch, Mongodb, Spring Boot, Microservices, Python, Ruby, Cassandra
Certifications:
Shaping-Up-With-Angular-Js
Shaping-Up-With-Angular-Js (Link)

Akash Bansal

Akash Bansal Photo 4

Akash Bansal

Akash Bansal Photo 5

Entrepreneur And Startup Mentor

Akash Bansal Photo 6
Location:
San Francisco, CA
Industry:
Internet
Work:
Kinderlime - Santa Clara, CA since Jul 2011
Co-founder and CEO
Education:
Indian Institute of Technology, Kanpur
B.Tech, Electrical Engineering University of Southern California
Master of Science, Computer Engineering
Skills:
Product Management, Mobile Devices, Entrepreneurship, Mobile Applications, Start Ups, System Architecture, Strategy, Software Development, Ruby on Rails, Business Development, Mobile Platforms, Pre Sales, Ip, Low Power Design, High Performance Computing, Serdes
Interests:
Social Media
Education
Mobile
Child Care

Akash Bansal

Akash Bansal Photo 7

Akash Bansal

Akash Bansal Photo 8
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Phones & Addresses

Name
Addresses
Phones
Akash Bansal
887 Blossom Dr, Santa Clara, CA 95050
408-260-9650
Akash Bansal
395 Ano Nuevo Ave #416, Sunnyvale, CA 94085
408-733-0248
Akash Bansal
395 Ano Nuevo Ave, Sunnyvale, CA 94085
408-733-0248
Akash Bansal
San Jose, CA
408-260-9650
Akash Bansal
Atlanta, GA
404-963-6374
Akash Bansal
39800 Fremont Blvd, Fremont, CA 94538
510-979-1109
Akash Bansal
4475 Park Sommers Way, San Jose, CA 95136
408-224-6076
Akash Bansal
46750 Fremont Blvd, Fremont, CA 94538

Publications

Us Patents

Asynchronous Transfer Mode Traffic Shapers

US Patent:
6198723, Mar 6, 2001
Filed:
Apr 14, 1998
Appl. No.:
9/060228
Inventors:
Bidyut Parruck - San Jose CA
Pramod B. Phadke - Mumbai, IN
Sachin N. Pradhan - Nigadi, IN
Akash Bansal - San Jose CA
Kishalay Haldar - San Jose CA
Assignee:
Paxonet Communications, Inc. - Fremont CA
International Classification:
H04J 316
H04L 1256
US Classification:
370230
Abstract:
The invention relates, in one embodiment, a computer-implemented method for shaping the output of cells on an output path of a data transmitting device. The data transmitting device is configured for switching the cells from a plurality of input paths to the output path to a network. In one embodiment the method includes sorting a plurality of queues, each queue including a plurality of cells associated with a communication device. The plurality of queues are arranged according to a weight and a data rate associated with each plurality of cells resulting in a plurality of sorted queues of queues. An aggregate output of cells from each sorted queue of queues is regulated based upon the data rates of the queues of the each sorted queue of queues. And, the output of the aggregate output of cells from each sorted queue of queues is regulated based upon the weights of the each sorted queue of queues, such that the scheduled output is coupled to the output path. The scheduled output conforms to a plurality of characteristics of the network, such that the network is efficiently used to carry the cells from the plurality of input paths to a plurality of communication devices.

High-Speed Signaling Systems And Methods With Adaptable, Continuous-Time Equalization

US Patent:
2015007, Mar 19, 2015
Filed:
Nov 25, 2014
Appl. No.:
14/552598
Inventors:
- Sunnyvale CA, US
Brian S. Leibowitz - San Francisco CA, US
Jade M. Kizer - Fort Collins CO, US
Thomas H. Greer - Chapel Hill NC, US
Akash Bansal - Santa Clara CA, US
International Classification:
H04B 1/12
H04L 25/03
US Classification:
375233
Abstract:
A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

Asynchronous Transfer Mode Traffic Shapers

US Patent:
7002916, Feb 21, 2006
Filed:
Jan 2, 2001
Appl. No.:
09/753797
Inventors:
Bidyut Parruck - San Jose CA, US
Pramod B. Phadke - Sion (East) Mumbai, IN
Sachin N. Pradhan - Nigadi, IN
Akash Bansal - San Jose CA, US
Kishalay Haldar - San Jose CA, US
Assignee:
Conexant Systems, Inc. - Newport Beach CA
Raza Microelectronics, Inc. - Cupertino CA
International Classification:
H04J 1/16
H04L 12/28
US Classification:
370235, 37039542, 370412
Abstract:
The invention relates, in one embodiment, a computer-implemented method for shaping the output of cells on an output path of a data transmitting device. The data transmitting device is configured for switching the cells from a plurality of input paths to the output path to a network. In one embodiment the method includes sorting a plurality of queues, each queue including a plurality of cells associated with a communication device. The plurality of queues are arranged according to a weight and a data rate associated with each plurality of cells resulting in a plurality of sorted queues of queues. An aggregate output of cells from each sorted queue of queues is regulated based upon the data rates of the queues of the each sorted queue of queues. And, the output of the aggregate output of cells from each sorted queue of queues is regulated based upon the weights of the each sorted queue of queues, such that the scheduled output is coupled to the output path. The scheduled output conforms to a plurality of characteristics of the network, such that the network is efficiently used to carry the cells from the plurality of input paths to a plurality of communication devices.

High Capacity Memory Systems

US Patent:
2015008, Mar 26, 2015
Filed:
Dec 20, 2012
Appl. No.:
14/386561
Inventors:
- Sunnyvale CA, US
Ely K. Tsern - Los Altos CA, US
Brian S. Leibowitz - San Francisco CA, US
Wayne Frederick Ellis - Campbell CA, US
Akash Bansal - Santa Clara CA, US
John Welsford Brooks - San Jose CA, US
Kishore Ven Kasamsetty - Cupertino CA, US
International Classification:
G06F 13/42
G06F 13/16
G11C 7/10
US Classification:
711149
Abstract:
In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

Timing-Drift Calibration

US Patent:
2015009, Apr 9, 2015
Filed:
Dec 15, 2014
Appl. No.:
14/570773
Inventors:
- Sunnyvale CA, US
Wayne F. Ellis - Campbell CA, US
Akash Bansal - Santa Clara CA, US
International Classification:
G11C 8/18
G11C 7/22
G11C 29/02
US Classification:
3652331
Abstract:
The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.

Error Detection And Recovery Of Data In Striped Channels

US Patent:
7246303, Jul 17, 2007
Filed:
Mar 24, 2003
Appl. No.:
10/396177
Inventors:
Akash Bansal - Sunnyvale CA, US
Jaisimha Bannur - Sunnyvale CA, US
Anujan Varma - Santa Cruz CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
F06F 11/00
G01R 31/28
H03M 13/00
US Classification:
714800, 714704, 714760, 714712
Abstract:
In general, in one aspect, the disclosure describes an apparatus that includes a transmission module to split a data segment into a plurality of data stripes and transmit each data stripe over an associated data channel. The plurality of data channels are organized into at least one group and each group has an associated parity channel to transmit a parity stripe generated based on the data stripes within the group. The apparatus also includes a reception module to receive the plurality of data stripes and the at least one parity stripe. The apparatus further includes a controller to control the operation of the apparatus.

Protocol For Memory Power-Mode Control

US Patent:
2015010, Apr 16, 2015
Filed:
Dec 17, 2014
Appl. No.:
14/573323
Inventors:
- Sunnyvale CA, US
Wayne S. Richardson - Saratoga CA, US
Akash Bansal - Santa Clara CA, US
Frederick A. Ware - Los Altos Hills CA, US
Lawrence Lai - San Jose CA, US
Kishore Ven Kasamsetty - Cupertino CA, US
International Classification:
G11C 11/406
G11C 11/4074
US Classification:
365222
Abstract:
In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Timing-Drift Calibration

US Patent:
2015013, May 14, 2015
Filed:
Jan 20, 2015
Appl. No.:
14/601078
Inventors:
- Sunnyvale CA, US
Wayne F. Ellis - Campbell CA, US
Akash Bansal - Santa Clara CA, US
International Classification:
G11C 8/18
G11C 7/22
US Classification:
3652331
Abstract:
The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.

FAQ: Learn more about Akash Bansal

Where does Akash Bansal live?

Santa Clara, CA is the place where Akash Bansal currently lives.

How old is Akash Bansal?

Akash Bansal is 52 years old.

What is Akash Bansal date of birth?

Akash Bansal was born on 1971.

What is Akash Bansal's email?

Akash Bansal has email address: aban***@alltel.net. Note that the accuracy of this email may vary and this is subject to privacy laws and restrictions.

What is Akash Bansal's telephone number?

Akash Bansal's known telephone numbers are: 412-908-0835, 510-687-1679, 408-733-0248, 510-979-1109, 408-224-6076, 408-260-9650. However, these numbers are subject to change and privacy restrictions.

How is Akash Bansal also known?

Akash Bansal is also known as: I Bansal, Bansal Akash. These names can be aliases, nicknames, or other names they have used.

Who is Akash Bansal related to?

Known relatives of Akash Bansal are: Vikas Bansal, Kailash Jayaswal, Archana Jayaswal, Arpana Jayaswal. This information is based on available public records.

What are Akash Bansal's alternative names?

Known alternative names for Akash Bansal are: Vikas Bansal, Kailash Jayaswal, Archana Jayaswal, Arpana Jayaswal. These can be aliases, maiden names, or nicknames.

What is Akash Bansal's current residential address?

Akash Bansal's current known residential address is: 887 Blossom Dr, Santa Clara, CA 95050. Please note this is subject to privacy laws and may not be current.

What are the previous addresses of Akash Bansal?

Previous addresses associated with Akash Bansal include: 3695 Stevenson Blvd, Fremont, CA 94538; 395 Ano Nuevo Ave, Sunnyvale, CA 94085; 39800 Fremont Blvd, Fremont, CA 94538; 4475 Park Sommers Way, San Jose, CA 95136; 46750 Fremont Blvd, Fremont, CA 94538. Remember that this information might not be complete or up-to-date.

Possible Relatives

Deepak Bansal Dhruv Bansal Dinesh Bansal Abhishek Bansal Gaurav Bansal Gunjan Bansal Jai Bansal Akash Kumar Akash Mohan Akash Singh

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